| Message ID | 20250124001032.1073926-1-michael@anarch128.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | x86-disas: port x86-mini disassembler to QEMU | expand |
On 1/24/25 13:10, Michael Clark wrote: > this metadata is based on x86-csv with numerous inaccuracies > fixed plus conversion of legacy instructions to a new LEX format. > this metadata has been fuzz-tested against the LLVM disassembler > for x86-64 with 64-bit ISA coverage in the order of ~99.9%. adding someone from AMD into this thread. I should say disassembly for ~99.9% of the Intel ISA in 64-bit mode. as I did not get to transcribing the AMD extensions yet. I did make a somewhat complete list of instructions that includes AMD extensions: https://github.com/michaeljclark/x86/blob/trunk/doc/x86_desc.md that table can be used to get a list of missing AMD instructions. in fact, I have a patch to x86-tablegen.py that does that. note SSE instructions paired with VEX extension start with lower case v so they will sort properly. and that file is grouped by extension instead of listed in alphabetical order of all possible orders. the version of x86-tablegen in the repo in the first message in this thread has additional features. it can read instruction descriptions to print fancy documentation in Markdown-like format. this is truncated for the email because it needs a 132 column line printer, as opposed to a 72 column line printer like emails. ./scripts/x86_tablegen.py --print-fancy-insn [AND] # r/m AND sign-extend ib. | opcode | encoding | |:-------------------------------------|:------------------------------| | AND r8/m8,r8 | lex.wb 20 /r lock | | AND rw/mw,rw | lex.wx 21 /r lock | | AND r8,r8/m8 | lex.wb 22 /r | | AND rw,rw/mw | lex.wx 23 /r | | AND al,ib | lex.wn 24 ib | | AND aw,iw | lex.wx 25 iw | | AND r8/m8,ib | lex.wb 80 /4 ib lock | | AND rw/mw,iw | lex.wx 81 /4 iw lock | | AND rw/mw,ib | lex.wx 83 /4 ib lock | |:-------------------------------------|:------------------------------| i'd appreciate if someone from AMD could contribute data for the AMD extensions, or donate hardware. ;D the interest in AVX-512 was because I have an old Intel 7980XE PC and TCG doesn't/didn't support AVX-512 so I thought I would write another one. I note there is `tcg_out_evex_opc` but I have not seen that code. the original code in x86-mini is external and is by-file MIT-licensed. so I would appreciate if folks that want to help with this could patch the original repo instead of making code that I can't use. like you are doing for Berkeley SoftFloat. thanks, Michael.