[qemu,0/5] hw/cxl: Cleanups and interleave support.

Message

Jonathan Cameron Feb. 3, 2025, 4:19 p.m. UTC

First set of CXL updates for the 10.0 cycle.
- Mixture of cleanup and hardening against a repeat of recent MSI-X
  numbering bug.
- Expanded interleave support (been on my tree a long time)

Whilst I think these are in a good state, review always welcome.

Li Zhijian (4):
  hw/cxl: Introduce CXL_T3_MSIX_VECTOR enumeration
  hw/mem/cxl_type3: Add paired msix_uninit_exclusive_bar() call
  hw/mem/cxl_type3: Fix special_ops memory leak on
    msix_init_exclusive_bar() failure
  hw/mem/cxl_type3: Ensure errp is set on realization failure

Yao Xingtao (1):
  mem/cxl_type3: support 3, 6, 12 and 16 interleave ways

 include/hw/cxl/cxl_device.h  |  4 ++--
 hw/cxl/cxl-component-utils.c |  9 ++++++--
 hw/cxl/cxl-device-utils.c    | 12 ++++------
 hw/cxl/switch-mailbox-cci.c  |  4 +++-
 hw/mem/cxl_type3.c           | 45 +++++++++++++++++++++++++-----------
 5 files changed, 48 insertions(+), 26 deletions(-)