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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:11 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 0/9] target/arm: Implement SEL2 physical and virtual timers Date: Tue, 4 Feb 2025 12:50:00 +0000 Message-Id: <20250204125009.2281315-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patchset is a respin of Alex's patches, with some extra fixes for bugs I discovered along the way in our existing code (and a bit of refactoring to make the fixes straightforward). It is: Based-on: 20250130182309.717346-1-peter.maydell@linaro.org ("target/arm: Clean up some corner cases of sysreg traps") because it wants to use the renamed CP_ACCESS_* constants that that patchset introduced. The bugfixes are not super exciting as they mostly are oddball corner cases, but I've cc'd them to stable anyway. The actual implementation of the missing SEL2 timers also should go to stable. Alex Bennée (4): target/arm: Implement SEL2 physical and virtual timers target/arm: document the architectural names of our GTIMERs hw/arm: enable secure EL2 timers for virt machine hw/arm: enable secure EL2 timers for sbsa machine Peter Maydell (5): target/arm: Apply correct timer offset when calculating deadlines target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses target/arm: Refactor handling of timer offset for direct register accesses include/hw/arm/bsa.h | 2 + target/arm/cpu.h | 2 + target/arm/gtimer.h | 14 +- target/arm/internals.h | 5 +- hw/arm/sbsa-ref.c | 2 + hw/arm/virt.c | 2 + target/arm/cpu.c | 4 + target/arm/helper.c | 324 ++++++++++++++++++++++++++++++------- target/arm/tcg/op_helper.c | 8 +- 9 files changed, 296 insertions(+), 67 deletions(-)