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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a1b8471sm23415105e9.37.2025.02.12.07.43.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:43:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore Date: Wed, 12 Feb 2025 16:43:25 +0100 Message-ID: <20250212154333.28644-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some boards based on Cortex-A9MP / Cortex-A15MP do not explicit the number of external GIC IRQs, using some (implicit) default value, not always trivial to figure out. Change that by removing the default value, requiring MPCore objects to be created with the "num-irq" set. Since v1: - Remove generic comments (Peter) Philippe Mathieu-Daudé (8): hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs hw/arm/realview: Specify explicitly the GIC has 64 external IRQs hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs hw/cpu/arm_mpcore: Remove default values for GIC external IRQs hw/arm/exynos4210.c | 10 ++++++++-- hw/arm/highbank.c | 8 ++++---- hw/arm/realview.c | 11 +++++++++-- hw/arm/vexpress.c | 7 +++++-- hw/arm/xilinx_zynq.c | 43 ++++++++++++++++++++++--------------------- hw/cpu/a15mpcore.c | 18 ++++++++++++------ hw/cpu/a9mpcore.c | 18 ++++++++++++------ 7 files changed, 72 insertions(+), 43 deletions(-)