[0/6] amd_iommu: Fixes to align with AMDVi specification

Message

Alejandro Jimenez March 11, 2025, 3:24 p.m. UTC

Correct mistakes in bitmasks, offsets, decoding of fields, and behavior that
do not match the latest AMD I/O Virtualization Technology (IOMMU)
Specification.  These bugs do not trigger problems today in the limited mode
of operation supported by the AMD vIOMMU (passthrough), but upcoming
functionality and tests will require them (and additional fixes).

These are all minor and hopefully not controversial fixes, so I am sending
them out at this time to separate them from later series adding
functionality. It is unclear how relevant these changes will be to stable
releases considering the state of the AMD vIOMMU, but the fixes on this
series should be simple enough to apply, so I Cc'd stable for consideration.

Thank you,
Alejandro

Alejandro Jimenez (6):
  amd_iommu: Fix Miscellanous Information Register 0 offsets
  amd_iommu: Fix Device ID decoding for INVALIDATE_IOTLB_PAGES command
  amd_iommu: Update bitmasks representing DTE reserved fields
  amd_iommu: Fix masks for Device Table Address Register
  amd_iommu: Fix the calculation for Device Table size
  amd_iommu: Do not assume passthrough translation for devices with
    DTE[TV]=0

 hw/i386/amd_iommu.c | 103 ++++++++++++++++++++++++--------------------
 hw/i386/amd_iommu.h |  25 ++++++-----
 2 files changed, 71 insertions(+), 57 deletions(-)


base-commit: 5136598e2667f35ef3dc1d757616a266bd5eb3a2