[0/1,v2,RISCV/RVV] Generate strided vector loads/stores with tcg nodes.

Message

Paolo Savini March 12, 2025, 3:55 p.m. UTC

Previous version:

- PATCH v1: https://lore.kernel.org/all/[e-mail]/ 

Follwing the suggestion in the following review by Daniel Barboza:

https://lore.kernel.org/all/[e-mail]/

we simplified the emulation by tcg nodes of such a complex operation as strided
loads/stores by breaking it into two separate functions.
One function implements the loop that performs the main load/store operation
with the supporting logic to address the vector elements with the right stride
and to fill with ones the inactive elements in the case of a load.
The second function implements the loop that sets to 1 the tail bytes if we
are in a tail agnostic regime.

Cc: Richard Handerson <[e-mail]>
Cc: Palmer Dabbelt <[e-mail]>
Cc: Alistair Francis <[e-mail]>
Cc: Bin Meng <[e-mail]>
Cc: Weiwei Li <[e-mail]>
Cc: Daniel Henrique Barboza <[e-mail]>
Cc: Liu Zhiwei <[e-mail]>
Cc: Helene Chelin <[e-mail]>
Cc: Nathan Egge <[e-mail]>
Cc: Max Chou <[e-mail]>
Cc: Jeremy Bennett <[e-mail]>
Cc: Craig Blackmore <[e-mail]>


Paolo Savini (1):
  [RISC-V/RVV] Generate strided vector loads/stores with tcg nodes.

 target/riscv/insn_trans/trans_rvv.c.inc | 323 ++++++++++++++++++++----
 1 file changed, 273 insertions(+), 50 deletions(-)