mbox series

[PATCHv2,00/17] ARM Secure EL2 extension

Message ID 5554493.MhkbZ0Pkbq@basile.remlab.net (mailing list archive)
Headers show
Series ARM Secure EL2 extension | expand

Message

Rémi Denis-Courmont Nov. 9, 2020, 1:56 p.m. UTC 
The following changes since commit 193f51ddcf1d87d725f1dfd51b8a95351c910e8f:

  Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-fixes-20201109' into staging (2020-11-09 10:10:49 +0000)

are available for review.

Changes since version 1:
- Add the first patch which was accidentally dropped.
- Try to address comments from Peter and Richard.

----------------------------------------------------------------
Rémi Denis-Courmont (17):
      target/arm: remove redundant tests
      target/arm: add arm_is_el2_enabled() helper
      target/arm: use arm_is_el2_enabled() where applicable
      target/arm: use arm_hcr_el2_eff() where applicable
      target/arm: factor MDCR_EL2 common handling
      target/arm: declare new AA64PFR0 bit-fields
      target/arm: add 64-bit S-EL2 to EL exception table
      target/arm: return the stage 2 index for stage 1
      target/arm: add MMU stage 1 for Secure EL2
      target/arm: add ARMv8.4-SEL2 system registers
      target/arm: do S1_ptw_translate() before address space lookup
      target/arm: secure stage 2 translation regime
      target/arm: handle VMID change in secure state
      target/arm: set HPFAR_EL2.NS on secure stage 2 faults
      target/arm: add ARMv8.4-SEL2 extension
      target/arm: enable Secure EL2 in max CPU
      target/arm: refactor vae1_tlbmask()

 target/arm/cpu-param.h     |   2 +-
 target/arm/cpu.c           |  10 +-
 target/arm/cpu.h           |  92 ++++++++--
 target/arm/cpu64.c         |   1 +
 target/arm/helper-a64.c    |   8 +-
 target/arm/helper.c        | 421 ++++++++++++++++++++++++++++++---------------
 target/arm/internals.h     |  54 +++++-
 target/arm/op_helper.c     |   4 +-
 target/arm/tlb_helper.c    |   3 +
 target/arm/translate-a64.c |   4 +
 target/arm/translate.c     |   6 +-
 target/arm/translate.h     |   1 +
 12 files changed, 426 insertions(+), 180 deletions(-)

Comments

no-reply@patchew.org Nov. 9, 2020, 2:36 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/5554493.MhkbZ0Pkbq@basile.remlab.net/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 5554493.MhkbZ0Pkbq@basile.remlab.net
Subject: [PATCHv2 00/17] ARM Secure EL2 extension
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20201022111302.8105-1-pankaj.gupta.linux@gmail.com -> patchew/20201022111302.8105-1-pankaj.gupta.linux@gmail.com
 - [tag update]      patchew/20201106235109.7066-1-peter.maydell@linaro.org -> patchew/20201106235109.7066-1-peter.maydell@linaro.org
 * [new tag]         patchew/5554493.MhkbZ0Pkbq@basile.remlab.net -> patchew/5554493.MhkbZ0Pkbq@basile.remlab.net
Switched to a new branch 'test'
d67dda8 target/arm: refactor vae1_tlbmask()
c3bfa38 target/arm: enable Secure EL2 in max CPU
794bf9f target/arm: add ARMv8.4-SEL2 extension
551e1e9 target/arm: set HPFAR_EL2.NS on secure stage 2 faults
2a31d5d target/arm: handle VMID change in secure state
f9b1072 target/arm: secure stage 2 translation regime
cf8f578 target/arm: do S1_ptw_translate() before address space lookup
ac77aef target/arm: add ARMv8.4-SEL2 system registers
8281b30 target/arm: add MMU stage 1 for Secure EL2
fb293c5 target/arm: return the stage 2 index for stage 1
d58b56e target/arm: add 64-bit S-EL2 to EL exception table
e5fdf26 target/arm: declare new AA64PFR0 bit-fields
d684ea4 target/arm: factor MDCR_EL2 common handling
2f79a14 target/arm: use arm_hcr_el2_eff() where applicable
840c8da target/arm: use arm_is_el2_enabled() where applicable
4cdb5a3 target/arm: add arm_is_el2_enabled() helper
0601131 target/arm: remove redundant tests

=== OUTPUT BEGIN ===
1/17 Checking commit 06011319d1cf (target/arm: remove redundant tests)
2/17 Checking commit 4cdb5a3d8a2f (target/arm: add arm_is_el2_enabled() helper)
WARNING: Block comments use a leading /* on a separate line
#21: FILE: target/arm/cpu.h:2043:
+/* Return true if the current security state has AArch64 EL2 or AArch32 Hyp.

WARNING: Block comments should align the * on each line
#23: FILE: target/arm/cpu.h:2045:
+ * This corresponds to the pseudocode EL2Enabled()
+  */

total: 0 errors, 2 warnings, 28 lines checked

Patch 2/17 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/17 Checking commit 840c8da0faca (target/arm: use arm_is_el2_enabled() where applicable)
4/17 Checking commit 2f79a14cc521 (target/arm: use arm_hcr_el2_eff() where applicable)
WARNING: line over 80 characters
#80: FILE: target/arm/helper.c:10356:
+        if ((arm_hcr_el2_eff(env) & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) {

total: 0 errors, 1 warnings, 79 lines checked

Patch 4/17 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/17 Checking commit d684ea4ba83f (target/arm: factor MDCR_EL2 common handling)
6/17 Checking commit e5fdf2693a6c (target/arm: declare new AA64PFR0 bit-fields)
7/17 Checking commit d58b56ecf73f (target/arm: add 64-bit S-EL2 to EL exception table)
WARNING: Block comments use a leading /* on a separate line
#30: FILE: target/arm/helper.c:9008:
+       {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 2,  2, -1,  1 },},},

WARNING: Block comments use a leading /* on a separate line
#31: FILE: target/arm/helper.c:9009:
+      {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1,  1,  1 },},

WARNING: Block comments use a leading /* on a separate line
#32: FILE: target/arm/helper.c:9010:
+       {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 2,  2,  2,  1 },},},},

WARNING: Block comments use a leading /* on a separate line
#37: FILE: target/arm/helper.c:9013:
+      {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3,  3,  3 },},

WARNING: Block comments use a leading /* on a separate line
#38: FILE: target/arm/helper.c:9014:
+       {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3,  3,  3 },},},},},

WARNING: Block comments use a leading /* on a separate line
#51: FILE: target/arm/op_helper.c:652:
+        /* Requesting a trap to EL2 when we're in EL3 is

total: 0 errors, 6 warnings, 30 lines checked

Patch 7/17 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/17 Checking commit fb293c5c257b (target/arm: return the stage 2 index for stage 1)
9/17 Checking commit 8281b3008c85 (target/arm: add MMU stage 1 for Secure EL2)
10/17 Checking commit ac77aef51d34 (target/arm: add ARMv8.4-SEL2 system registers)
11/17 Checking commit cf8f578fb8b8 (target/arm: do S1_ptw_translate() before address space lookup)
12/17 Checking commit f9b1072a2302 (target/arm: secure stage 2 translation regime)
ERROR: code indent should never use tabs
#18: FILE: target/arm/cpu.h:171:
+#define VTCR_NSW^I(1u << 29)$

ERROR: code indent should never use tabs
#19: FILE: target/arm/cpu.h:172:
+#define VTCR_NSA^I(1u << 30)$

ERROR: code indent should never use tabs
#20: FILE: target/arm/cpu.h:173:
+#define VSTCR_SW^IVTCR_NSW$

ERROR: code indent should never use tabs
#21: FILE: target/arm/cpu.h:174:
+#define VSTCR_SA^IVTCR_NSA$

WARNING: Block comments use a leading /* on a separate line
#390: FILE: target/arm/internals.h:983:
+        /* Note: Secure stage 2 nominally shares fields from VTCR_EL2, but

ERROR: braces {} are necessary for all arms of this statement
#405: FILE: target/arm/internals.h:1200:
+        if (s2_mmu_idx != NULL)
[...]

total: 5 errors, 1 warnings, 355 lines checked

Patch 12/17 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

13/17 Checking commit 2a31d5df0802 (target/arm: handle VMID change in secure state)
14/17 Checking commit 551e1e971371 (target/arm: set HPFAR_EL2.NS on secure stage 2 faults)
15/17 Checking commit 794bf9f61cbc (target/arm: add ARMv8.4-SEL2 extension)
WARNING: Block comments use a leading /* on a separate line
#101: FILE: target/arm/helper.c:3396:
+        /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in

ERROR: spaces required around that '|' (ctx:VxV)
#119: FILE: target/arm/helper.c:3668:
+    if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & (SCR_NS|SCR_EEL2))) {
                                                                  ^

total: 1 errors, 1 warnings, 137 lines checked

Patch 15/17 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

16/17 Checking commit c3bfa38083de (target/arm: enable Secure EL2 in max CPU)
17/17 Checking commit d67dda8443c1 (target/arm: refactor vae1_tlbmask())
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/5554493.MhkbZ0Pkbq@basile.remlab.net/testing.checkpatch/?type=message.
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