From patchwork Fri Jul 27 14:37:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10547275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED596112B for ; Fri, 27 Jul 2018 14:44:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9C572B27F for ; Fri, 27 Jul 2018 14:44:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CA3B72852D; Fri, 27 Jul 2018 14:44:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5C5E22852D for ; Fri, 27 Jul 2018 14:44:24 +0000 (UTC) Received: from localhost ([::1]:41632 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fj3yh-0000Es-Mc for patchwork-qemu-devel@patchwork.kernel.org; Fri, 27 Jul 2018 10:44:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34368) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fj3sH-0003FC-Ny for qemu-devel@nongnu.org; Fri, 27 Jul 2018 10:37:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fj3sG-0008Iq-OK for qemu-devel@nongnu.org; Fri, 27 Jul 2018 10:37:45 -0400 Received: from greensocs.com ([193.104.36.180]:50604) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fj3sB-0008Ad-Ff; Fri, 27 Jul 2018 10:37:39 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 61D094434A7; Fri, 27 Jul 2018 16:37:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532702250; bh=oKkibQCsQWapdPkP4zGCcL7dmTPjrZpJ/zBixSp29OY=; h=From:To:Cc:Subject:Date; b=YFia5PFvBPZVi9f7X4EwYr8YTr5fzQ2lDtFwNvfqMbN2ujv3NOpp8qN/IbLwkq26f TwaPfViPGyup3SmnHv0tcZzN0yAQbtNIkdTCxkolbziAxgE/Q67m6CK1XtzuxmE+vl Rw9bNumQdPPaHPf93CE0T5QBEVpT4wQOpkgrVrp0= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=gvzxIhcN; dkim=pass (1024-bit key) header.d=greensocs.com header.b=gvzxIhcN Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xpAR8q9YXP2B; Fri, 27 Jul 2018 16:37:29 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 8AE98428994; Fri, 27 Jul 2018 16:37:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532702249; bh=oKkibQCsQWapdPkP4zGCcL7dmTPjrZpJ/zBixSp29OY=; h=From:To:Cc:Subject:Date; b=gvzxIhcNCrrflPQlf32RuBvEkJg4l488vKEno0DTdcnrkUtvATDsu8HJ2QkHmitHL iZWZfk47D2fE9VOyXgAcS9PG6DdNcA8QOSK5MjNRsLQPIZSDAj+3gM2FQNC55CXE3+ gIRJxQUaHPOIJJceXVLdIIuNsZwfq7nBDydQkljs= Received: from kouign-amann.hive.antfield.fr (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: damien.hedde@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 20713400DC8; Fri, 27 Jul 2018 16:37:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532702249; bh=oKkibQCsQWapdPkP4zGCcL7dmTPjrZpJ/zBixSp29OY=; h=From:To:Cc:Subject:Date; b=gvzxIhcNCrrflPQlf32RuBvEkJg4l488vKEno0DTdcnrkUtvATDsu8HJ2QkHmitHL iZWZfk47D2fE9VOyXgAcS9PG6DdNcA8QOSK5MjNRsLQPIZSDAj+3gM2FQNC55CXE3+ gIRJxQUaHPOIJJceXVLdIIuNsZwfq7nBDydQkljs= From: Damien Hedde To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 16:37:19 +0200 Message-Id: X-Mailer: git-send-email 2.18.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 0/6] Clock and power gating support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair@alistair23.me, mark.burton@greensocs.com, saipava@xilinx.com, qemu-arm@nongnu.org, Damien Hedde , pbonzini@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This set of patches add support for power and clock gating in device objects. It adds two booleans to the state, one for power state and one of clock state. The state is controlled trough 2 functions, one for power and one for clock. Two new methods *power_update* and *clock_update* is added to the device class which are called on state change and can be overriden. Default behavior is the following: + Device are initialized in powered and clocked state. + reset method is called when powering-up. This set also implements this support in the cadence_uart device in the xilinx_zynq platform as an example. The 1st patch add the gating support to the base device object. The 2nd patch add functions to act on a whole bus tree. The 3rd patch overrides the *power/clock_update* methods for sysbus devices to enable/disable the memory regions according to the state. The 4th patch updates the cadence_uart device and the 5th patch adds uart clock gating support to the zynq clock controller *slcr*. The 6th patch finally adds the support to *xilinx-zynq* machine. This is an RFC as it remains open questions about the strategy to implement this kind of support. Here's some remarks: + This set adds power and clock, some reset state could be added too. Although default behavior is tricky to implement because there is many kind of reset (eg syncronous/asynchronous). + I used methods which require to store links of controlled devices in clock/power controller. Using gpios or specifics child objects to achieve the same functionnaly is possible. + Power and clock state could be merged to a single 3-state (powered-off, unclocked, on) since clock does not really matters when powered-off. + Regarding migration, it's problematic to add the VMStateDescription in qdev so we let it to the specialization (eg in cadence_uart) to handle it. Is this a problem ? Anyway support of clock gating requires modification in specialization. It may not be necessary to store the gating states in each device, since it is stored already in the controller registers. But we would then have to set the gating state of devices in the controller's post_load which may occurs before or after devices VMState load: It seems tricky to ensure device state is correct at the end if gating update do side-effects. + theses patches add a simple vision (1 power, 1 clock). Devices can be more complex. For example, the zynq's uart has 2 independant clock domains: 1 for the bus interface, 1 for uart operations. I'm not sure if we should keep 1, add the bus/device separation or do something more configurable on a per-specialization basis. Feel free to comment, Damien Hedde (6): qdev: add a power and clock gating support qdev: add power/clock gating control on bus tree sysbus: Specialize gating_update to enable/disable memory regions cadence_uart: add clock/power gating support zynq_slcr: add uart clock gating and soft reset support xilinx_zynq: add uart clock gating support include/hw/qdev-core.h | 50 ++++++++++++++++++++ include/hw/sysbus.h | 3 ++ hw/arm/xilinx_zynq.c | 20 +++++--- hw/char/cadence_uart.c | 25 +++++++++- hw/core/qdev.c | 103 +++++++++++++++++++++++++++++++++++++++++ hw/core/sysbus.c | 39 ++++++++++++++++ hw/misc/zynq_slcr.c | 63 +++++++++++++++++++++++++ 7 files changed, 296 insertions(+), 7 deletions(-)