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X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [RFC v2 00/24] Add RISC-V TCG backend support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , "richard.henderson@linaro.org" , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Alistair Francis (24): elf.h: Add the RISCV ELF magic numbers linux-user: Add host dependency for RISC-V 32-bit linux-user: Add host dependency for RISC-V 64-bit exec: Add RISC-V GCC poison macro riscv: Add the tcg-target header file riscv: Add the tcg target registers riscv: tcg-target: Add support for the constraints riscv: tcg-target: Add the immediate encoders riscv: tcg-target: Add the instruction emitters riscv: tcg-target: Add the relocation functions riscv: tcg-target: Add the mov and movi instruction riscv: tcg-target: Add the extract instructions riscv: tcg-target: Add the out load and store instructions riscv: tcg-target: Add branch and jump instructions riscv: tcg-target: Add slowpath load and store instructions riscv: tcg-target: Add direct load and store instructions riscv: tcg-target: Add the out op decoder riscv: tcg-target: Add the prologue generation and register the JIT riscv: tcg-target: Add the target init code tcg: Add RISC-V cpu signal handler dias: Add RISC-V support configure: Add support for building RISC-V host WIP: Add missing instructions WIP: Try to patch longer branches accel/tcg/user-exec.c | 75 ++ configure | 12 +- disas.c | 10 +- include/elf.h | 55 + include/exec/poison.h | 1 + linux-user/host/riscv32/hostdep.h | 11 + linux-user/host/riscv64/hostdep.h | 11 + tcg/riscv/tcg-target.h | 173 +++ tcg/riscv/tcg-target.inc.c | 1890 +++++++++++++++++++++++++++++ 9 files changed, 2234 insertions(+), 4 deletions(-) create mode 100644 linux-user/host/riscv32/hostdep.h create mode 100644 linux-user/host/riscv64/hostdep.h create mode 100644 tcg/riscv/tcg-target.h create mode 100644 tcg/riscv/tcg-target.inc.c