mbox series

[v1,00/23] Add RISC-V TCG backend support

Message ID cover.1544643238.git.alistair.francis@wdc.com (mailing list archive)
Headers show
Series Add RISC-V TCG backend support | expand

Message

Alistair Francis Dec. 12, 2018, 7:42 p.m. UTC 
This patch set adds RISC-V backend support to QEMU. This is based on
Michael Clark's original work with extra work on top.
This has been somewhat tested and can run other architecture softmmu
code. It seems that any complex OS will eventually hang, but we can
run the BIOS and OS startup code for a number of different operating
systems.
I haven't tested linux user support at all yet. I think Michael had that
working reliably though and hopefully my changes haven't broken it.
There are still some todos in the code (there are missing instructions
and byte swapping) but these should assert instead of generating invalid
code.
As this is all new work (so can't cause regressions) I'm starting the
patch series process with what we have so far. That way others can help
contribute and test. If anyone has strong feelings for missing functionality
let me know and we can work on adding that before this is merged.
This branch can be found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend-upstream.next
v1:
 - Fix long jump with slowpath load/stores
RFC v3:
 - Update the MAINTAINERS file
 - Enusre that RISC-V 32-bit works
 - More changes based on Richard's feedback and contributions
RFC v2:
 - A large number of changes based on Richard's feedback

Alistair Francis (23):
  elf.h: Add the RISCV ELF magic numbers
  linux-user: Add host dependency for RISC-V 32-bit
  linux-user: Add host dependency for RISC-V 64-bit
  exec: Add RISC-V GCC poison macro
  riscv: Add the tcg-target header file
  riscv: Add the tcg target registers
  riscv: tcg-target: Add support for the constraints
  riscv: tcg-target: Add the immediate encoders
  riscv: tcg-target: Add the instruction emitters
  riscv: tcg-target: Add the relocation functions
  riscv: tcg-target: Add the mov and movi instruction
  riscv: tcg-target: Add the extract instructions
  riscv: tcg-target: Add the out load and store instructions
  riscv: tcg-target: Add the add2 and sub2 instructions
  riscv: tcg-target: Add branch and jump instructions
  riscv: tcg-target: Add slowpath load and store instructions
  riscv: tcg-target: Add direct load and store instructions
  riscv: tcg-target: Add the out op decoder
  riscv: tcg-target: Add the prologue generation and register the JIT
  riscv: tcg-target: Add the target init code
  tcg: Add RISC-V cpu signal handler
  dias: Add RISC-V support
  configure: Add support for building RISC-V host

 MAINTAINERS                       |    3 +
 accel/tcg/user-exec.c             |   75 ++
 configure                         |   12 +-
 disas.c                           |   10 +-
 include/elf.h                     |   55 +
 include/exec/poison.h             |    1 +
 linux-user/host/riscv32/hostdep.h |   11 +
 linux-user/host/riscv64/hostdep.h |   11 +
 tcg/riscv/tcg-target.h            |  175 +++
 tcg/riscv/tcg-target.inc.c        | 1929 +++++++++++++++++++++++++++++
 10 files changed, 2278 insertions(+), 4 deletions(-)
 create mode 100644 linux-user/host/riscv32/hostdep.h
 create mode 100644 linux-user/host/riscv64/hostdep.h
 create mode 100644 tcg/riscv/tcg-target.h
 create mode 100644 tcg/riscv/tcg-target.inc.c

Comments

Richard Henderson Dec. 12, 2018, 11:33 p.m. UTC | #1 
On 12/12/18 1:42 PM, Alistair Francis wrote:
> As this is all new work (so can't cause regressions) I'm starting the
> patch series process with what we have so far. That way others can help
> contribute and test. If anyone has strong feelings for missing functionality
> let me know and we can work on adding that before this is merged.

I'd be ok merging this immediately after the bswap patches currently queued on
my tcg-next-2 branch.  Which for you just means defining
TCG_TARGET_HAS_MEMORY_BSWAP to 0 and fixing the one MAINTAINERS entry.

Anything else can be fixed or improved via normal development.


r~
Alistair Francis Dec. 13, 2018, 12:41 a.m. UTC | #2 
On 12/12/2018 3:33 pm, Richard Henderson wrote:
> On 12/12/18 1:42 PM, Alistair Francis wrote:
>> As this is all new work (so can't cause regressions) I'm starting the
>> patch series process with what we have so far. That way others can help
>> contribute and test. If anyone has strong feelings for missing functionality
>> let me know and we can work on adding that before this is merged.
> 
> I'd be ok merging this immediately after the bswap patches currently queued on
> my tcg-next-2 branch.  Which for you just means defining
> TCG_TARGET_HAS_MEMORY_BSWAP to 0 and fixing the one MAINTAINERS entry.
> 
> Anything else can be fixed or improved via normal development.

Awesome!

I have fixed the maintainers file and defined 
TCG_TARGET_HAS_MEMORY_BSWAP to 0 (no effect yet) in my tree.

Unless anyone else has any comments I'm just going to sit on these 
patches until your branch is merged then I'll send a v2.

Alistair

> 
> 
> r~
>
no-reply@patchew.org Dec. 13, 2018, 2:48 a.m. UTC | #3 
Patchew URL: https://patchew.org/QEMU/cover.1544643238.git.alistair.francis@wdc.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: cover.1544643238.git.alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH v1 00/23]  Add RISC-V TCG backend support

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
9b5c932 configure: Add support for building RISC-V host
fb15898 dias: Add RISC-V support
00c84d1 tcg: Add RISC-V cpu signal handler
6add641 riscv: tcg-target: Add the target init code
1558363 riscv: tcg-target: Add the prologue generation and register the JIT
eb2e81d riscv: tcg-target: Add the out op decoder
3810670 riscv: tcg-target: Add direct load and store instructions
3f9c9cb riscv: tcg-target: Add slowpath load and store instructions
effb6ef riscv: tcg-target: Add branch and jump instructions
6a4e141 riscv: tcg-target: Add the add2 and sub2 instructions
b275d63 riscv: tcg-target: Add the out load and store instructions
6739758 riscv: tcg-target: Add the extract instructions
5949cfc riscv: tcg-target: Add the mov and movi instruction
d304333 riscv: tcg-target: Add the relocation functions
417d704 riscv: tcg-target: Add the instruction emitters
0df8498 riscv: tcg-target: Add the immediate encoders
78dfa82 riscv: tcg-target: Add support for the constraints
de25c73 riscv: Add the tcg target registers
24cb807 riscv: Add the tcg-target header file
bc2a324 exec: Add RISC-V GCC poison macro
2d2a64a linux-user: Add host dependency for RISC-V 64-bit
19d241f linux-user: Add host dependency for RISC-V 32-bit
0bf04f5 elf.h: Add the RISCV ELF magic numbers

=== OUTPUT BEGIN ===
Checking PATCH 1/23: elf.h: Add the RISCV ELF magic numbers...
Checking PATCH 2/23: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

total: 0 errors, 1 warnings, 18 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/23: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

total: 0 errors, 1 warnings, 18 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/23: exec: Add RISC-V GCC poison macro...
Checking PATCH 5/23: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

WARNING: architecture specific defines should be avoided
#56: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32

total: 0 errors, 2 warnings, 182 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/23: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 118 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/23: riscv: tcg-target: Add support for the constraints...
Checking PATCH 8/23: riscv: tcg-target: Add the immediate encoders...
Checking PATCH 9/23: riscv: tcg-target: Add the instruction emitters...
Checking PATCH 10/23: riscv: tcg-target: Add the relocation functions...
Checking PATCH 11/23: riscv: tcg-target: Add the mov and movi instruction...
Checking PATCH 12/23: riscv: tcg-target: Add the extract instructions...
Checking PATCH 13/23: riscv: tcg-target: Add the out load and store instructions...
Checking PATCH 14/23: riscv: tcg-target: Add the add2 and sub2 instructions...
Checking PATCH 15/23: riscv: tcg-target: Add branch and jump instructions...
Checking PATCH 16/23: riscv: tcg-target: Add slowpath load and store instructions...
Checking PATCH 17/23: riscv: tcg-target: Add direct load and store instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: tcg/riscv/tcg-target.inc.c:1192:
+    tcg_insn_unit *label_ptr[1];
                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#145: FILE: tcg/riscv/tcg-target.inc.c:1263:
+    tcg_insn_unit *label_ptr[1];
                   ^

total: 2 errors, 0 warnings, 161 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 18/23: riscv: tcg-target: Add the out op decoder...
Checking PATCH 19/23: riscv: tcg-target: Add the prologue generation and register the JIT...
Checking PATCH 20/23: riscv: tcg-target: Add the target init code...
Checking PATCH 21/23: tcg: Add RISC-V cpu signal handler...
Checking PATCH 22/23: dias: Add RISC-V support...
WARNING: architecture specific defines should be avoided
#22: FILE: disas.c:526:
+#if defined(_ILP32) || (__riscv_xlen == 32)

total: 0 errors, 1 warnings, 16 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 23/23: configure: Add support for building RISC-V host...
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/cover.1544643238.git.alistair.francis@wdc.com/testing.checkpatch/?type=message.
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