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X-Received-From: 216.71.154.45 Subject: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V fixes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This series is another go at reducing the diff between the RISC-V fork (https://github.com/riscv/riscv-qemu/) and mainline QEMU. This is a small series with only a handful of changes as I don't want to have to deal with too many conflicts all at once and I don't want to create too much conflict with the ongoing decode tree work. Once the decode tree work goes in we can look at rebasing the changes in the RISC-V fork that touch translate.c. Michael Clark (4): RISC-V: Add hartid and \n to interrupt logging RISC-V: Fix CLINT timecmp low 32-bit writes RISC-V: Fix PLIC pending bitfield reads RISC-V: Enable second UART on sifive_e and sifive_u Nathaniel Graff (1): sifive_uart: Implement interrupt pending register hw/riscv/sifive_clint.c | 8 ++++---- hw/riscv/sifive_e.c | 5 ++--- hw/riscv/sifive_plic.c | 2 +- hw/riscv/sifive_u.c | 5 ++--- hw/riscv/sifive_uart.c | 24 +++++++++++++++++++----- include/hw/riscv/sifive_uart.h | 3 +++ target/riscv/cpu_helper.c | 18 ++++++++++-------- 7 files changed, 41 insertions(+), 24 deletions(-)