| Message ID | cover.1552699115.git.alistair.francis@wdc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Upstream RISC-V fork patches, part 4 | expand |
On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis <alistair23@gmail.com> wrote: > > On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis > <Alistair.Francis@wdc.com> wrote: > > > > v3: > > - Add a patch to remove some dead code > > - Rebase on master > > v2: > > - Add a patch for SiFive U SMP support > > - Rebase on master > > > > Alistair Francis (3): > > riscv: pmp: Log pmp access errors as guest errors > > riscv: sifive_u: Allow up to 4 CPUs to be created > > target/riscv: Remove unused struct > > > > Kito Cheng (1): > > RISC-V: linux-user support for RVE ABI > > > > Michael Clark (8): > > RISC-V: Replace __builtin_popcount with ctpop8 in PLIC > > RISC-V: Allow interrupt controllers to claim interrupts > > RISC-V: Remove unnecessary disassembler constraints > > elf: Add RISC-V PSABI ELF header defines > > RISC-V: Change local interrupts from edge to level > > RISC-V: Add support for vectored interrupts > > RISC-V: Convert trap debugging to trace events > > RISC-V: Update load reservation comment in do_interrupt @Palmer Any chance this can go in for 4.0? It's just bug fixes that have been on list for a while. Without this series u-boot SMP won't work in QEMU, see here: https://lists.denx.de/pipermail/u-boot/2019-March/360899.html Alistair > > Sorry, this series should be v3 in the title. I won't resend it, just pretend :) > > Alistair > > > > > Makefile.objs | 1 + > > disas/riscv.c | 138 ----------------------------- > > hw/riscv/sifive_plic.c | 19 +++- > > hw/riscv/sifive_u.c | 5 +- > > include/elf.h | 10 +++ > > linux-user/riscv/cpu_loop.c | 15 +++- > > target/riscv/cpu.c | 6 -- > > target/riscv/cpu.h | 6 ++ > > target/riscv/cpu_helper.c | 168 +++++++++++++++--------------------- > > target/riscv/cpu_user.h | 3 +- > > target/riscv/csr.c | 22 ++--- > > target/riscv/pmp.c | 20 +++-- > > target/riscv/trace-events | 2 + > > 13 files changed, 148 insertions(+), 267 deletions(-) > > create mode 100644 target/riscv/trace-events > > > > -- > > 2.21.0 > >
On Mon, 18 Mar 2019 17:33:38 PDT (-0700), alistair23@gmail.com wrote: > On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis <alistair23@gmail.com> wrote: >> >> On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis >> <Alistair.Francis@wdc.com> wrote: >> > >> > v3: >> > - Add a patch to remove some dead code >> > - Rebase on master >> > v2: >> > - Add a patch for SiFive U SMP support >> > - Rebase on master >> > >> > Alistair Francis (3): >> > riscv: pmp: Log pmp access errors as guest errors >> > riscv: sifive_u: Allow up to 4 CPUs to be created >> > target/riscv: Remove unused struct >> > >> > Kito Cheng (1): >> > RISC-V: linux-user support for RVE ABI >> > >> > Michael Clark (8): >> > RISC-V: Replace __builtin_popcount with ctpop8 in PLIC >> > RISC-V: Allow interrupt controllers to claim interrupts >> > RISC-V: Remove unnecessary disassembler constraints >> > elf: Add RISC-V PSABI ELF header defines >> > RISC-V: Change local interrupts from edge to level >> > RISC-V: Add support for vectored interrupts >> > RISC-V: Convert trap debugging to trace events >> > RISC-V: Update load reservation comment in do_interrupt > > @Palmer > > Any chance this can go in for 4.0? It's just bug fixes that have been > on list for a while. Without this series u-boot SMP won't work in > QEMU, see here: > https://lists.denx.de/pipermail/u-boot/2019-March/360899.html That was my plan. Since they're all bug fixes I was more worried about getting everything together on the decodetree front. I'm hoping to get another PR out later this week that collects all the bug fixes we have floating around for rc1. > > Alistair > >> >> Sorry, this series should be v3 in the title. I won't resend it, just pretend :) >> >> Alistair >> >> > >> > Makefile.objs | 1 + >> > disas/riscv.c | 138 ----------------------------- >> > hw/riscv/sifive_plic.c | 19 +++- >> > hw/riscv/sifive_u.c | 5 +- >> > include/elf.h | 10 +++ >> > linux-user/riscv/cpu_loop.c | 15 +++- >> > target/riscv/cpu.c | 6 -- >> > target/riscv/cpu.h | 6 ++ >> > target/riscv/cpu_helper.c | 168 +++++++++++++++--------------------- >> > target/riscv/cpu_user.h | 3 +- >> > target/riscv/csr.c | 22 ++--- >> > target/riscv/pmp.c | 20 +++-- >> > target/riscv/trace-events | 2 + >> > 13 files changed, 148 insertions(+), 267 deletions(-) >> > create mode 100644 target/riscv/trace-events >> > >> > -- >> > 2.21.0 >> >
On Mon, Mar 18, 2019 at 8:41 PM Palmer Dabbelt <palmer@sifive.com> wrote: > > On Mon, 18 Mar 2019 17:33:38 PDT (-0700), alistair23@gmail.com wrote: > > On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis <alistair23@gmail.com> wrote: > >> > >> On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis > >> <Alistair.Francis@wdc.com> wrote: > >> > > >> > v3: > >> > - Add a patch to remove some dead code > >> > - Rebase on master > >> > v2: > >> > - Add a patch for SiFive U SMP support > >> > - Rebase on master > >> > > >> > Alistair Francis (3): > >> > riscv: pmp: Log pmp access errors as guest errors > >> > riscv: sifive_u: Allow up to 4 CPUs to be created > >> > target/riscv: Remove unused struct > >> > > >> > Kito Cheng (1): > >> > RISC-V: linux-user support for RVE ABI > >> > > >> > Michael Clark (8): > >> > RISC-V: Replace __builtin_popcount with ctpop8 in PLIC > >> > RISC-V: Allow interrupt controllers to claim interrupts > >> > RISC-V: Remove unnecessary disassembler constraints > >> > elf: Add RISC-V PSABI ELF header defines > >> > RISC-V: Change local interrupts from edge to level > >> > RISC-V: Add support for vectored interrupts > >> > RISC-V: Convert trap debugging to trace events > >> > RISC-V: Update load reservation comment in do_interrupt > > > > @Palmer > > > > Any chance this can go in for 4.0? It's just bug fixes that have been > > on list for a while. Without this series u-boot SMP won't work in > > QEMU, see here: > > https://lists.denx.de/pipermail/u-boot/2019-March/360899.html > > That was my plan. Since they're all bug fixes I was more worried about getting > everything together on the decodetree front. I'm hoping to get another PR out > later this week that collects all the bug fixes we have floating around for > rc1. Awesome! Thanks for getting all the patches in. Alistair > > > > > Alistair > > > >> > >> Sorry, this series should be v3 in the title. I won't resend it, just pretend :) > >> > >> Alistair > >> > >> > > >> > Makefile.objs | 1 + > >> > disas/riscv.c | 138 ----------------------------- > >> > hw/riscv/sifive_plic.c | 19 +++- > >> > hw/riscv/sifive_u.c | 5 +- > >> > include/elf.h | 10 +++ > >> > linux-user/riscv/cpu_loop.c | 15 +++- > >> > target/riscv/cpu.c | 6 -- > >> > target/riscv/cpu.h | 6 ++ > >> > target/riscv/cpu_helper.c | 168 +++++++++++++++--------------------- > >> > target/riscv/cpu_user.h | 3 +- > >> > target/riscv/csr.c | 22 ++--- > >> > target/riscv/pmp.c | 20 +++-- > >> > target/riscv/trace-events | 2 + > >> > 13 files changed, 148 insertions(+), 267 deletions(-) > >> > create mode 100644 target/riscv/trace-events > >> > > >> > -- > >> > 2.21.0 > >> >