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25 Jul 2019 11:53:14 -0700 IronPort-SDR: 3QKObQufGOY7T2CyWkHUH/mud/mOLaT//1cKbulfwdlJCdF1tHE74PCgIFaOaK5IkoMfELQJ2m /saAyrCOubQbuyiRnuQAwFhk2IOEqYFHI8VUaGEEjo2vXZrvujJ9kqpUAfaHwBW9IxUk96ooVQ KwIoZ9KmM4pjWr0IESmT+vJ1hLlf5Mfi4Fdw+0JHgXiY+iICXH6P7IUbmS9yzmd3h3raKVfZ2S EPJ1lOnQRCIUo0cI0eEeAltNTWr6GHDIYWaC4yOMuVDEx4IjYMh/ZF4tSSOTjHC40ye9fwQAD1 2dE= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip02.wdc.com with ESMTP; 25 Jul 2019 11:55:03 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 25 Jul 2019 11:51:58 -0700 Message-Id: X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.154.45 Subject: [Qemu-devel] [PATCH-4.2 v1 0/6] RISC-V: Hypervisor prep work part 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The first four patches are ones that I have pulled out of my original Hypervisor series at an attempt to reduce the number of patches in the series. These four patches all make sense without the Hypervisor series so can be merged seperatley and will reduce the review burden of the next version of the patches. The fifth patch is a prep patch for the new v0.4 Hypervisor spec. The final patch is unreleated to Hypervisor that I'm just slipping in here because it seems easier then sending it by itself. Alistair Francis (5): target/riscv: Don't set write permissions on dirty PTEs target/riscv: Remove strict perm checking for CSR R/W riscv: plic: Remove unused interrupt functions target/riscv: Create function to test if FP is enabled target/riscv: Update the Hypervisor CSRs to v0.4 Atish Patra (1): target/riscv: Fix Floating Point register names hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 6 +++++- target/riscv/cpu_bits.h | 35 +++++++++++++++++----------------- target/riscv/cpu_helper.c | 16 ++++++++++++---- target/riscv/csr.c | 22 ++++++++++----------- 7 files changed, 50 insertions(+), 52 deletions(-)