| Message ID | cover.1567750222.git.alistair@alistair23.me (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add the STM32F405 and Netduino Plus 2 machine | expand |
Patchew URL: https://patchew.org/QEMU/cover.1567750222.git.alistair@alistair23.me/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v4 0/6] Add the STM32F405 and Netduino Plus 2 machine
Message-id: cover.1567750222.git.alistair@alistair23.me
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
8b0ecd4 hw/arm: Add the Netduino Plus 2
407f73f hw/arm: Add the STM32F4xx SoC
512fff3 hw/misc: Add the STM32F4xx EXTI device
2caad5c hw/misc: Add the STM32F4xx Sysconfig device
955f060 target/arm: Allow setting M mode entry and sp
d81d27f armv7m: Allow entry information to be returned
=== OUTPUT BEGIN ===
1/6 Checking commit d81d27f0996a (armv7m: Allow entry information to be returned)
WARNING: line over 80 characters
#24: FILE: hw/arm/armv7m.c:309:
+uint64_t armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
WARNING: line over 80 characters
#52: FILE: include/hw/arm/boot.h:36:
+uint64_t armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
total: 0 errors, 2 warnings, 30 lines checked
Patch 1/6 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/6 Checking commit 955f06078662 (target/arm: Allow setting M mode entry and sp)
3/6 Checking commit 2caad5c67035 (hw/misc: Add the STM32F4xx Sysconfig device)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#77:
new file mode 100644
ERROR: suspect code indent for conditional statements (4, 7)
#135: FILE: hw/misc/stm32f4xx_syscfg.c:54:
+ if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {
+ qemu_set_irq(s->gpio_out[irq], level);
WARNING: line over 80 characters
#222: FILE: hw/misc/stm32f4xx_syscfg.c:141:
+ VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState, SYSCFG_NUM_EXTICR),
total: 1 errors, 2 warnings, 285 lines checked
Patch 3/6 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/6 Checking commit 512fff3fab76 (hw/misc: Add the STM32F4xx EXTI device)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#50:
new file mode 100644
total: 0 errors, 1 warnings, 281 lines checked
Patch 4/6 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/6 Checking commit 407f73fb3229 (hw/arm: Add the STM32F4xx SoC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#57:
new file mode 100644
total: 0 errors, 1 warnings, 404 lines checked
Patch 5/6 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/6 Checking commit 8b0ecd413bdc (hw/arm: Add the Netduino Plus 2)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 86 lines checked
Patch 6/6 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/cover.1567750222.git.alistair@alistair23.me/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
On Fri, 6 Sep 2019 at 07:10, Alistair Francis <alistair@alistair23.me> wrote: > > > Now that the Arm-M4 CPU has been added to QEMU we can add the Netduino > Plus 2 machine. This is very similar to the STM32F205 and Netduino 2 SoC > and machine. > > v4: > - Rebase on master > v3: > - Remove custom reset handler > - Add init-entry and init-sp properties > - Rebase on master (including Kconfig changes) > v2: > - Reorder patchset > - Return the kernel entry point instead of using a pointer > - Address Peter's comments > > > Alistair Francis (6): > armv7m: Allow entry information to be returned > target/arm: Allow setting M mode entry and sp > hw/misc: Add the STM32F4xx Sysconfig device > hw/misc: Add the STM32F4xx EXTI device > hw/arm: Add the STM32F4xx SoC > hw/arm: Add the Netduino Plus 2 What are the changes for setting initial SP and PC for? Why is this SoC special? Is it different from the stm32f205 SoC we model already? I'm not in general a fan of individual board models having their own custom behaviour for -kernel. The inconsistencies between architectures and between A- and M- profile are awkward enough as it is... thanks -- PMM
On Wed, Sep 11, 2019, at 11:49 AM, Peter Maydell wrote: > On Fri, 6 Sep 2019 at 07:10, Alistair Francis <alistair@alistair23.me> wrote: > > > > > > Now that the Arm-M4 CPU has been added to QEMU we can add the Netduino > > Plus 2 machine. This is very similar to the STM32F205 and Netduino 2 SoC > > and machine. > > > > v4: > > - Rebase on master > > v3: > > - Remove custom reset handler > > - Add init-entry and init-sp properties > > - Rebase on master (including Kconfig changes) > > v2: > > - Reorder patchset > > - Return the kernel entry point instead of using a pointer > > - Address Peter's comments > > > > > > Alistair Francis (6): > > armv7m: Allow entry information to be returned > > target/arm: Allow setting M mode entry and sp > > hw/misc: Add the STM32F4xx Sysconfig device > > hw/misc: Add the STM32F4xx EXTI device > > hw/arm: Add the STM32F4xx SoC > > hw/arm: Add the Netduino Plus 2 > > What are the changes for setting initial SP and PC for? If it's not set the the guest code jumps into some broken address and crashes at boot. > Why is this SoC special? Is it different from the > stm32f205 SoC we model already? From memory the STM32F205 might have the same issue. It just wasn't a big problem as my STM32F2xx tests were targeting QEMU while the STM32F4xx isn't. > > I'm not in general a fan of individual board models having > their own custom behaviour for -kernel. The inconsistencies > between architectures and between A- and M- profile are > awkward enough as it is... I do see it as a pain as well, but I'm not sure what else to do to fix it. Alistair > > thanks > -- PMM > >
On Wed, 11 Sep 2019 at 15:07, Alistair <alistair@alistair23.me> wrote: > > On Wed, Sep 11, 2019, at 11:49 AM, Peter Maydell wrote: > > On Fri, 6 Sep 2019 at 07:10, Alistair Francis <alistair@alistair23.me> wrote: > > > Now that the Arm-M4 CPU has been added to QEMU we can add the Netduino > > > Plus 2 machine. This is very similar to the STM32F205 and Netduino 2 SoC > > > and machine. > > What are the changes for setting initial SP and PC for? > > If it's not set the the guest code jumps into some broken address and crashes at boot. If this happens then something else is wrong. The CPU should be reading the initial SP and PC from the vector table that's in the guest image. If it's not doing that then we need to figure out why (perhaps we're not setting the correct value for the vector table base register?) thanks -- PMM