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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id g22sm9059783pgb.82.2020.07.25.08.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jul 2020 08:03:33 -0700 (PDT) From: Zong Li To: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 0/4] Fix some PMP implementations Date: Sat, 25 Jul 2020 23:03:23 +0800 Message-Id: X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=zong.li@sifive.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zong Li Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This patch set contains the fixes for wrong index of pmpcfg CSR on rv64, and the pmp range in CSR function table. After 3rd version of this patch series, we also fix the PMP issues such as wrong physical address translation and ignoring PMP checking. Changed in v5: - Pick the suggestion which was lost in last version. Changed in v4: - Refine the implementation. Suggested by Bin Meng. - Add fix for PMP checking was ignored. Changed in v3: - Refine the implementation. Suggested by Bin Meng. - Add fix for wrong pphysical address translation. Changed in v2: - Move out the shifting operation from loop. Suggested by Bin Meng. Zong Li (4): target/riscv: Fix the range of pmpcfg of CSR funcion table target/riscv/pmp.c: Fix the index offset on RV64 target/riscv: Fix the translation of physical address target/riscv: Change the TLB page size depends on PMP entries. target/riscv/cpu_helper.c | 13 ++++++-- target/riscv/csr.c | 2 +- target/riscv/pmp.c | 63 ++++++++++++++++++++++++++++++++++++++- target/riscv/pmp.h | 2 ++ 4 files changed, 75 insertions(+), 5 deletions(-)