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14 Dec 2020 12:17:40 -0800 IronPort-SDR: TonXMkvEKwrmXh9wWmoRUfihFLFkIYxsFhsZPH4p3iYCknq6NgElY6Sqb828kg598DyGUZEDVs U6bToDgj2idXfUW2z8ShgvHkSc/A5V6hgy8SgSOgCPl/C6WdSPAH8cGPVuFwEStnHBzOmZVvR0 EKqxDKReEuvHjC3pUY+JJ5qZhZf72AjP0BVbIWjSpaTMJwmayEL7MecbSlmYm4s2Q9QKmtT9tm BrsxSkB5kAyFSHCpHXwhTxwtB6oVCN34xC/AP55XhkmwP6pANI+3NJ/UEXVJKIherOV7nouvOf Tq4= WDCIronportException: Internal Received: from cnf006900.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.52]) by uls-op-cesaip02.wdc.com with ESMTP; 14 Dec 2020 12:33:56 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Date: Mon, 14 Dec 2020 12:33:56 -0800 Message-Id: X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=61015ee87=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running Hypervisors with different xlen guests). This series is a step toward removing some of those to allow us to use 32-bit CPUs on 64-bit RISC-V targets. v3: - Address Richard's comments v2: - Rebase on the latest RISC-V tree Alistair Francis (15): hw/riscv: Expand the is 32-bit check to support more CPUs target/riscv: Add a TYPE_RISCV_CPU_BASE CPU riscv: spike: Remove target macro conditionals riscv: virt: Remove target macro conditionals hw/riscv: boot: Remove compile time XLEN checks hw/riscv: virt: Remove compile time XLEN checks hw/riscv: spike: Remove compile time XLEN checks hw/riscv: sifive_u: Remove compile time XLEN checks target/riscv: fpu_helper: Match function defs in HELPER macros target/riscv: Add a riscv_cpu_is_32bit() helper function target/riscv: Specify the XLEN for CPUs target/riscv: cpu: Remove compile time XLEN checks target/riscv: cpu_helper: Remove compile time XLEN checks target/riscv: csr: Remove compile time XLEN checks target/riscv: cpu: Set XLEN independently from target include/hw/riscv/boot.h | 8 +- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 4 +- hw/riscv/boot.c | 67 +++++++++------ hw/riscv/sifive_u.c | 57 ++++++------ hw/riscv/spike.c | 50 ++++++----- hw/riscv/virt.c | 36 ++++---- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu_helper.c | 12 +-- target/riscv/csr.c | 176 ++++++++++++++++++++------------------ target/riscv/fpu_helper.c | 16 ++-- 13 files changed, 295 insertions(+), 235 deletions(-)