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16 Dec 2020 10:05:59 -0800 IronPort-SDR: Ns5h6xa216anIqSotJTRdqjfPykY4XmB5PLNc6ZYxsy/ahQXSBx88scUzNejD1dpOWtQgLF6RQ pFzpvFirZZBzBb1SelNIAH8ssDhLpsdwzlkfKCLG2gE9T3keynm/2PQH8zcLT4i7CQobnkMpVU t2cXjPyfgIw+J6bxQofs06lLE7LIwjTgAjsRpOmiE21Zw4makcXG5NfH1pGyVgyvuXIrnOUCGW QqfC7RZLWuVi+UdhR7WtIE3KXRwisfqhkwYyvs2s2eVSmjogMYLZqsSgSs/hSrLIgLH/kxuHza Ml0= WDCIronportException: Internal Received: from 1996l72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.67]) by uls-op-cesaip02.wdc.com with ESMTP; 16 Dec 2020 10:22:24 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 00/16] RISC-V: Start to remove xlen preprocess Date: Wed, 16 Dec 2020 10:22:23 -0800 Message-Id: X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=612374860=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running Hypervisors with different xlen guests). This series is a step toward removing some of those to allow us to use 32-bit CPUs on 64-bit RISC-V targets. v4: - Add a commit that converts the machine 32-bit check to use the CPU v3: - Address Richard's comments v2: - Rebase on the latest RISC-V tree Alistair Francis (16): hw/riscv: Expand the is 32-bit check to support more CPUs target/riscv: Add a TYPE_RISCV_CPU_BASE CPU riscv: spike: Remove target macro conditionals riscv: virt: Remove target macro conditionals hw/riscv: boot: Remove compile time XLEN checks hw/riscv: virt: Remove compile time XLEN checks hw/riscv: spike: Remove compile time XLEN checks hw/riscv: sifive_u: Remove compile time XLEN checks target/riscv: fpu_helper: Match function defs in HELPER macros target/riscv: Add a riscv_cpu_is_32bit() helper function target/riscv: Specify the XLEN for CPUs target/riscv: cpu: Remove compile time XLEN checks target/riscv: cpu_helper: Remove compile time XLEN checks target/riscv: csr: Remove compile time XLEN checks target/riscv: cpu: Set XLEN independently from target hw/riscv: Use the CPU to determine if 32-bit include/hw/riscv/boot.h | 14 +-- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 4 +- target/riscv/helper.h | 24 ++---- hw/riscv/boot.c | 70 ++++++++------- hw/riscv/sifive_u.c | 59 +++++++------ hw/riscv/spike.c | 52 +++++------ hw/riscv/virt.c | 39 +++++---- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu_helper.c | 12 +-- target/riscv/csr.c | 176 ++++++++++++++++++++------------------ target/riscv/fpu_helper.c | 8 -- 14 files changed, 299 insertions(+), 263 deletions(-)