[v1,0/8] RISC-V: Steps towards running 32-bit guests on

Message

Alistair Francis April 2, 2021, 8:02 p.m. UTC

This is another step towards running 32-bit CPU code on the 64-bit
softmmu builds for RISC-V.

I have tested this and am able to run some 32-bit code, but eventually
hit some issue.  This series doesn't allow users to use 32-bit CPUs with
64-bit softmmu builds as it doesn't work yet. This series instead just
gets us a little closer to being able to and removes more hardcoded
macros so hopefully others also stop using them for new code.

Alistair Francis (8):
  target/riscv: Remove the hardcoded RVXLEN macro
  target/riscv: Remove the hardcoded SSTATUS_SD macro
  target/riscv: Remove the hardcoded HGATP_MODE macro
  target/riscv: Remove the hardcoded MSTATUS_SD macro
  target/riscv: Remove the hardcoded SATP_MODE macro
  target/riscv: Remove the unused HSTATUS_WPRI macro
  target/riscv: Remove an unused CASE_OP_32_64 macro
  target/riscv: Include RV32 instructions in RV64 build

 target/riscv/cpu.h            |  6 ----
 target/riscv/cpu_bits.h       | 44 ----------------------------
 target/riscv/insn16-32.decode | 24 ++++++++++++++++
 target/riscv/insn16-64.decode | 31 ++++++++++++++++++++
 target/riscv/cpu.c            |  6 +++-
 target/riscv/cpu_helper.c     | 51 +++++++++++++++++++++++++--------
 target/riscv/csr.c            | 54 +++++++++++++++++++++++++++--------
 target/riscv/monitor.c        | 22 ++++++++++----
 target/riscv/translate.c      | 43 ++++++++++++++++++++++------
 target/riscv/meson.build      |  7 +++--
 10 files changed, 197 insertions(+), 91 deletions(-)