[v2,0/5] target/riscv: Enhanced ISA extension checks

Message

Tsukasa OI May 15, 2022, 2:56 a.m. UTC

c.f.
<https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00221.html>

I was obviously drunk when finalizing PATCH v1.

[BUGS in PATCH v1 (fixed in v2)]
PATCH 1: My English was (or, "is"?) broken
         (commit subject and message is rewritten)
PATCH 4: Zfinx requirement test were in the wrong place
PATCH 5: Zfinx/F exclusivity test was completely wrong
         I meant Zfinx&&F but when finalizing my patchset, I somehow
         changed this place to Zfinx&&!F.




Tsukasa OI (5):
  target/riscv: Fix coding style on "G" expansion
  target/riscv: Disable "G" by default
  target/riscv: Change "G" expansion
  target/riscv: FP extension requirements
  target/riscv: Move/refactor ISA extension checks

 target/riscv/cpu.c | 63 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 46 insertions(+), 17 deletions(-)


base-commit: 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab