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[v4,0/2] Enhanced VSTART and VL checks for vector instructions

Message ID cover.1741573286.git.lc00631@tecorigin.com (mailing list archive)
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Series Enhanced VSTART and VL checks for vector instructions | expand

Message

Chao Liu March 10, 2025, 2:35 a.m. UTC 
Hi, Alistair:

I rebase both patches based on the riscv-to-apply.next branch and tested them.
https://github.com/alistair23/qemu/tree/riscv-to-apply.next

Only the first patch had two conflicts, which were resolved nicely,
and the second patch rebased fine, so you can review it again if necessary,
thanks!

PATCH v3 review:
https://lore.kernel.org/qemu-riscv/71f15782-ec28-4763-8197-c10ec12811ec@ventanamicro.com/

PATCH v2 review:
https://lore.kernel.org/qemu-devel/61e8f7d8-607a-4d63-b9dd-cfbfc840716e@ventanamicro.com/

PATCH v1 review:
https://lore.kernel.org/qemu-devel/CAKmqyKPFYxhK8PANOVzV3FMWxd79wZSJYLWkKOAgEMt_b2KvZA@mail.gmail.com/

--
Regards,
Chao

Chao Liu (2):
  target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to  accept vl as a
    parameter
  target/riscv: fix handling of nop for vstart >= vl in some vector
    instruction

 target/riscv/vcrypto_helper.c   | 32 ++++++-------
 target/riscv/vector_helper.c    | 83 ++++++++++++++++++---------------
 target/riscv/vector_internals.c |  4 +-
 target/riscv/vector_internals.h | 12 ++---
 4 files changed, 69 insertions(+), 62 deletions(-)