Show patches with: Submitter = Alistair Francis       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,03/15] target/riscv: Move the hfence instructions to the rvh decode RISC-V: Update the Hypervisor spec to v0.6 - - - --- 2020-04-26 Alistair Francis New
[v1,02/15] target/riscv: Report errors validating 2nd-stage PTEs RISC-V: Update the Hypervisor spec to v0.6 - - - --- 2020-04-26 Alistair Francis New
[v1,01/15] target/riscv: Set access as data_load when validating stage-2 PTEs RISC-V: Update the Hypervisor spec to v0.6 - - - --- 2020-04-26 Alistair Francis New
[for,5.0,v1,2/2] riscv: AND stage-1 and stage-2 protection flags RISC-V: Fix Hypervisor guest user space - 1 - --- 2020-03-26 Alistair Francis New
[for,5.0,v1,1/2] riscv: Don't use stage-2 PTE lookup protection flags RISC-V: Fix Hypervisor guest user space - 1 - --- 2020-03-26 Alistair Francis New
[PULL,1/1] device_tree: Add info message when dumping dtb to file [PULL,1/1] device_tree: Add info message when dumping dtb to file - 2 - --- 2020-03-20 Alistair Francis New
[PULL,0/1] DTC queue for 5.0 - - - --- 2020-03-20 Alistair Francis New
[v9,4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-18 Alistair Francis New
[v9,3/4] linux-user: Support futex_time64 linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-03-18 Alistair Francis New
[v9,2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64 linux-user: generate syscall_nr.sh for RISC-V - 2 - --- 2020-03-18 Alistair Francis New
[v9,1/4] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - 2 - --- 2020-03-18 Alistair Francis New
[v8,4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-13 Alistair Francis New
[v8,3/4] linux-user: Support futex_time64 linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-13 Alistair Francis New
[v8,2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64 linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-13 Alistair Francis New
[v8,1/4] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-13 Alistair Francis New
[v7,4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-12 Alistair Francis New
[v7,3/4] linux-user: Support futex_time64 linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-03-12 Alistair Francis New
[v7,2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64 linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-12 Alistair Francis New
[v7,1/4] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-12 Alistair Francis New
[v3,3/3] riscv/sifive_u: Add a serial property to the sifive_u machine [v3,1/3] riscv/sifive_u: Fix up file ordering - 2 - --- 2020-03-06 Alistair Francis New
[v3,2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC [v3,1/3] riscv/sifive_u: Fix up file ordering - 1 1 --- 2020-03-06 Alistair Francis New
[v3,1/3] riscv/sifive_u: Fix up file ordering [v3,1/3] riscv/sifive_u: Fix up file ordering - 1 - --- 2020-03-06 Alistair Francis New
[v6,4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-06 Alistair Francis New
[v6,3/4] linux-user: Support futex_time64 linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-03-06 Alistair Francis New
[v6,2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64 linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-06 Alistair Francis New
[v6,1/4] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-06 Alistair Francis New
[v5,3/3] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-05 Alistair Francis New
[v5,2/3] linux-user/syscall: Add support for clock_gettime64/clock_settime64 linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-03-05 Alistair Francis New
[v5,1/3] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-03-05 Alistair Francis New
[v2,3/3] riscv/sifive_u: Add a serial property to the sifive_u machine hw/riscv: Add a serial property to the sifive_u machine - 2 - --- 2020-03-04 Alistair Francis New
[v2,2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC hw/riscv: Add a serial property to the sifive_u machine - 1 1 --- 2020-03-04 Alistair Francis New
[v2,1/3] riscv/sifive_u: Fix up file ordering hw/riscv: Add a serial property to the sifive_u machine - - - --- 2020-03-04 Alistair Francis New
[v1,3/3] riscv/sifive_u: Add a serial property to the sifive_u machine hw/riscv: Add a serial property to the sifive_u machine - 2 - --- 2020-03-04 Alistair Francis New
[v1,2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC hw/riscv: Add a serial property to the sifive_u machine - - - --- 2020-03-04 Alistair Francis New
[v1,1/3] riscv/sifive_u: Fix up file ordering hw/riscv: Add a serial property to the sifive_u machine - - - --- 2020-03-04 Alistair Francis New
[v1,1/1] target/riscv: Don't set write permissions on dirty PTEs [v1,1/1] target/riscv: Don't set write permissions on dirty PTEs - 1 - --- 2020-03-04 Alistair Francis New
[v4,3/3] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-03-04 Alistair Francis New
[v4,2/3] linux-user/syscall: Add support for clock_gettime64/clock_settime64 linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-03-04 Alistair Francis New
[v4,1/3] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-03-04 Alistair Francis New
[v3,2/2] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-02-26 Alistair Francis New
[v3,1/2] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-02-26 Alistair Francis New
[v2,2/2] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-02-24 Alistair Francis New
[v2,1/2] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-02-24 Alistair Francis New
[v1,2/2] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel linux-user: generate syscall_nr.sh for RISC-V - - - --- 2020-02-20 Alistair Francis New
[v1,1/2] linux-user: Protect more syscalls linux-user: generate syscall_nr.sh for RISC-V - 1 - --- 2020-02-20 Alistair Francis New
[v2,35/35] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,32/35] target/riscv: Set htval and mtval2 on execptions Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,31/35] target/riscv: Raise the new execptions when 2nd stage translation fails Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,30/35] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,29/35] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,28/35] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,26/35] target/riscv: Disable guest FP support based on virtual status Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,25/35] target/riscv: Only set TB flags with FP status if enabled Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,24/35] target/riscv: Remove the hret instruction Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,23/35] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,22/35] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,21/35] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,20/35] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,19/35] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,18/35] target/riscv: Add support for virtual interrupt setting Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,17/35] target/riscv: Extend the SIP CSR to support virtulisation Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,16/35] target/riscv: Extend the MIE CSR to support virtulisation Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,15/35] target/riscv: Set VS bits in mideleg for Hyp extension Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,14/35] target/riscv: Add virtual register swapping function Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,13/35] target/riscv: Add Hypervisor machine CSRs accesses Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,12/35] target/riscv: Add Hypervisor virtual CSRs accesses Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,11/35] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,10/35] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,09/35] target/riscv: Print priv and virt in disas log Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,08/35] target/riscv: Fix CSR perm checking for HS mode Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,07/35] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,06/35] target/riscv: Add the virtulisation mode Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,05/35] target/riscv: Rename the H irqs to VS irqs Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,04/35] target/riscv: Add support for the new execption numbers Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,03/35] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v2,02/35] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension v0.5 - 2 - --- 2020-02-01 Alistair Francis New
[v2,01/35] target/riscv: Convert MIP CSR to target_ulong Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2020-02-01 Alistair Francis New
[v1,1/1] target/riscv: Correctly implement TSR trap [v1,1/1] target/riscv: Correctly implement TSR trap - 1 - --- 2020-01-21 Alistair Francis New
[v1,36/36] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,33/36] target/riscv: Set htval and mtval2 on execptions Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,32/36] target/riscv: Raise the new execptions when 2nd stage translation fails Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,31/36] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,30/36] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,29/36] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,28/36] target/riscv: Mark both sstatus and vsstatus as dirty Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,27/36] target/riscv: Disable guest FP support based on virtual status Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,26/36] target/riscv: Remove the hret instruction Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,25/36] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,24/36] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,23/36] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,21/36] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,20/36] target/riscv: Add support for virtual interrupt setting Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,18/36] target/riscv: Extend the MIE CSR to support virtulisation Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
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