Show patches with: Submitter = Stafford Horne       |    State = Action Required       |   211 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,v2,19/25] target/openrisc: Increase the TLB size - - - --- 2018-07-02 Stafford Horne New
[PULL,v2,18/25] target/openrisc: Stub out handle_mmu_fault for softmmu - - - --- 2018-07-02 Stafford Horne New
[PULL,v2,17/25] target/openrisc: Use identical sizes for ITLB and DTLB - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,16/25] target/openrisc: Fix cpu_mmu_index - - - --- 2018-07-02 Stafford Horne New
[PULL,v2,15/25] target/openrisc: Fix tlb flushing in mtspr - - - --- 2018-07-02 Stafford Horne New
[PULL,v2,14/25] target/openrisc: Reduce tlb to a single dimension - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,13/25] target/openrisc: Merge mmu_helper.c into mmu.c - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,12/25] target/openrisc: Remove indirect function calls for mmu - - - --- 2018-07-02 Stafford Horne New
[PULL,v2,11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,10/25] target/openrisc: Form the spr index from tcg - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,09/25] target/openrisc: Exit the TB after l.mtspr - - - --- 2018-07-02 Stafford Horne New
[PULL,v2,08/25] target/openrisc: Split out is_user - 2 - --- 2018-07-02 Stafford Horne New
[PULL,v2,07/25] target/openrisc: Link more translation blocks - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,06/25] target/openrisc: Fix singlestep_enabled - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP - 2 - --- 2018-07-02 Stafford Horne New
[PULL,v2,03/25] target/openrisc: Log interrupts - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,02/25] target/openrisc: Add print_insn_or1k - 1 - --- 2018-07-02 Stafford Horne New
[PULL,v2,01/25] target/openrisc: Fix mtspr shadow gprs - 1 - --- 2018-07-02 Stafford Horne New
[PULL,25/25] target/openrisc: Fix writes to interrupt mask register - 1 - --- 2018-07-02 Stafford Horne New
[PULL,24/25] target/openrisc: Fix delay slot exception flag to match spec - 1 - --- 2018-07-02 Stafford Horne New
[PULL,23/25] linux-user: Fix struct sigaltstack for openrisc - 1 - --- 2018-07-02 Stafford Horne New
[PULL,22/25] linux-user: Implement signals for openrisc - - - --- 2018-07-02 Stafford Horne New
[PULL,21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh - 1 - --- 2018-07-02 Stafford Horne New
[PULL,20/25] target/openrisc: Reorg tlb lookup - - - --- 2018-07-02 Stafford Horne New
[PULL,19/25] target/openrisc: Increase the TLB size - - - --- 2018-07-02 Stafford Horne New
[PULL,18/25] target/openrisc: Stub out handle_mmu_fault for softmmu - - - --- 2018-07-02 Stafford Horne New
[PULL,17/25] target/openrisc: Use identical sizes for ITLB and DTLB - 1 - --- 2018-07-02 Stafford Horne New
[PULL,16/25] target/openrisc: Fix cpu_mmu_index - - - --- 2018-07-02 Stafford Horne New
[PULL,15/25] target/openrisc: Fix tlb flushing in mtspr - - - --- 2018-07-02 Stafford Horne New
[PULL,14/25] target/openrisc: Reduce tlb to a single dimension - 1 - --- 2018-07-02 Stafford Horne New
[PULL,13/25] target/openrisc: Merge mmu_helper.c into mmu.c - 1 - --- 2018-07-02 Stafford Horne New
[PULL,12/25] target/openrisc: Remove indirect function calls for mmu - - - --- 2018-07-02 Stafford Horne New
[PULL,11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState - 1 - --- 2018-07-02 Stafford Horne New
[PULL,10/25] target/openrisc: Form the spr index from tcg - 1 - --- 2018-07-02 Stafford Horne New
[PULL,09/25] target/openrisc: Exit the TB after l.mtspr - - - --- 2018-07-02 Stafford Horne New
[PULL,07/25] target/openrisc: Link more translation blocks - 1 - --- 2018-07-02 Stafford Horne New
[PULL,06/25] target/openrisc: Fix singlestep_enabled - 1 - --- 2018-07-02 Stafford Horne New
[PULL,05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB - 1 - --- 2018-07-02 Stafford Horne New
[PULL,04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP - 2 - --- 2018-07-02 Stafford Horne New
[PULL,03/25] target/openrisc: Log interrupts - 1 - --- 2018-07-02 Stafford Horne New
[PULL,02/25] target/openrisc: Add print_insn_or1k - 1 - --- 2018-07-02 Stafford Horne New
[PULL,01/25] target/openrisc: Fix mtspr shadow gprs - 1 - --- 2018-07-02 Stafford Horne New
target/openrisc: Fix writes to interrupt mask register - 1 - --- 2018-07-01 Stafford Horne New
target/openrisc: Fix delay slot exception flag to match spec - 1 - --- 2018-07-01 Stafford Horne New
[PULL,v2,5/5] openrisc: Only kick cpu on timeout, not on update - 1 - --- 2017-10-20 Stafford Horne New
[PULL,v2,4/5] openrisc: Initial SMP support - 1 - --- 2017-10-20 Stafford Horne New
[PULL,v2,3/5] openrisc/cputimer: Perparation for Multicore - 1 - --- 2017-10-20 Stafford Horne New
[PULL,v2,2/5] target/openrisc: Make coreid and numcores variable - 1 - --- 2017-10-20 Stafford Horne New
[PULL,v2,1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) - 1 - --- 2017-10-20 Stafford Horne New
[PULL,5/5] openrisc: Only kick cpu on timeout, not on update - 1 - --- 2017-10-13 Stafford Horne New
[PULL,4/5] openrisc: Initial SMP support - 1 - --- 2017-10-13 Stafford Horne New
[PULL,3/5] openrisc/cputimer: Perparation for Multicore - 1 - --- 2017-10-13 Stafford Horne New
[PULL,2/5] target/openrisc: Make coreid and numcores variable - 1 - --- 2017-10-13 Stafford Horne New
[PULL,1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) - 1 - --- 2017-10-13 Stafford Horne New
[v2,5/5] openrisc: Only kick cpu on timeout, not on update - 1 - --- 2017-10-13 Stafford Horne New
[v2,4/5] openrisc: Initial SMP support - 1 - --- 2017-10-13 Stafford Horne New
[v2,3/5] openrisc/cputimer: Perparation for Multicore - 1 - --- 2017-10-13 Stafford Horne New
[v2,2/5] target/openrisc: Make coreid and numcores variable - 1 - --- 2017-10-13 Stafford Horne New
[v2,1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) - 1 - --- 2017-10-13 Stafford Horne New
[5/5] openrisc: Only kick cpu on timeout, not on update - 1 - --- 2017-08-23 Stafford Horne New
[4/5] openrisc: Initial SMP support - 1 - --- 2017-08-23 Stafford Horne New
[3/5] openrisc/cputimer: Perparation for Multicore - 1 - --- 2017-08-23 Stafford Horne New
[2/5] target/openrisc: Make coreid and numcores configurable in state - - - --- 2017-08-23 Stafford Horne New
[1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) - 1 - --- 2017-08-23 Stafford Horne New
[PULL,v2,11/11] target/openrisc: Support non-busy idle state using PMR SPR - 1 - --- 2017-05-04 Stafford Horne New
[PULL,v2,10/11] target/openrisc: Remove duplicate features property - - - --- 2017-05-04 Stafford Horne New
[PULL,v2,09/11] target/openrisc: Implement full vmstate serialization - - - --- 2017-05-04 Stafford Horne New
[PULL,v2,08/11] migration: Add VMSTATE_STRUCT_2DARRAY() - - - --- 2017-05-04 Stafford Horne New
[PULL,v2,07/11] target/openrisc: implement shadow registers - - - --- 2017-05-04 Stafford Horne New
[PULL,v2,06/11] migration: Add VMSTATE_UINTTL_2DARRAY() - - - --- 2017-05-04 Stafford Horne New
[PULL,v2,05/11] target/openrisc: add numcores and coreid support - 1 - --- 2017-05-04 Stafford Horne New
[PULL,v2,04/11] target/openrisc: Fixes for memory debugging - 1 - --- 2017-05-04 Stafford Horne New
[PULL,v2,03/11] target/openrisc: Implement EPH bit - - - --- 2017-05-04 Stafford Horne New
[PULL,v2,02/11] target/openrisc: Implement EVBAR register - - - --- 2017-05-04 Stafford Horne New
[PULL,v2,01/11] MAINTAINERS: Add myself as openrisc maintainer - 1 - --- 2017-05-04 Stafford Horne New
[PULL,11/11] target/openrisc: Support non-busy idle state using PMR SPR - 1 - --- 2017-04-30 Stafford Horne New
[PULL,10/11] target/openrisc: Remove duplicate features property - - - --- 2017-04-30 Stafford Horne New
[PULL,09/11] target/openrisc: Implement full vmstate serialization - - - --- 2017-04-30 Stafford Horne New
[PULL,08/11] migration: Add VMSTATE_STRUCT_2DARRAY() - - - --- 2017-04-30 Stafford Horne New
[PULL,07/11] target/openrisc: implement shadow registers - - - --- 2017-04-30 Stafford Horne New
[PULL,06/11] migration: Add VMSTATE_UINTTL_2DARRAY() - - - --- 2017-04-30 Stafford Horne New
[PULL,05/11] target/openrisc: add numcores and coreid support - 1 - --- 2017-04-30 Stafford Horne New
[PULL,04/11] target/openrisc: Fixes for memory debugging - 1 - --- 2017-04-30 Stafford Horne New
[PULL,03/11] target/openrisc: Implement EPH bit - - - --- 2017-04-30 Stafford Horne New
[PULL,02/11] target/openrisc: Implement EVBAR register - - - --- 2017-04-30 Stafford Horne New
[PULL,01/11] MAINTAINERS: Add myself as openrisc maintainer - 1 - --- 2017-04-30 Stafford Horne New
target/openrisc: Support non-busy idle state using PMR SPR - 1 - --- 2017-04-28 Stafford Horne New
[RFC,v2] target/openrisc: Support non-busy idle state using PMR SPR - - - --- 2017-04-25 Stafford Horne New
[v2,9/9] target/openrisc: Remove duplicate features property - - - --- 2017-04-23 Stafford Horne New
[v2,8/9] target/openrisc: Implement full vmstate serialization - - - --- 2017-04-23 Stafford Horne New
[v2,7/9] migration: Add VMSTATE_STRUCT_2DARRAY() - - - --- 2017-04-23 Stafford Horne New
[v2,6/9] target/openrisc: implement shadow registers - - - --- 2017-04-23 Stafford Horne New
[v2,5/9] migration: Add VMSTATE_UINTTL_2DARRAY() - - - --- 2017-04-23 Stafford Horne New
[v2,4/9] target/openrisc: add numcores and coreid support - 1 - --- 2017-04-23 Stafford Horne New
[v2,3/9] target/openrisc: Fixes for memory debugging - 1 - --- 2017-04-23 Stafford Horne New
[v2,2/9] target/openrisc: Implement EPH bit - - - --- 2017-04-23 Stafford Horne New
[v2,1/9] target/openrisc: Implement EVBAR register - - - --- 2017-04-23 Stafford Horne New
[RFC] target/openrisc: Support non-busy idle state using PMR SPR - - - --- 2017-04-23 Stafford Horne New
[7/7] target/openrisc: Implement full vmstate serialization - - - --- 2017-04-16 Stafford Horne New
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