Show patches with: Submitter = Artyom Tarasenko       |    State = Action Required       |   132 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[29/29] target-sparc: fix up Niagara machine - 1 - --- 2016-10-01 Artyom Tarasenko New
[28/29] target-sparc: move common cpu initialisation routines to sparc64.c - 1 - --- 2016-10-01 Artyom Tarasenko New
[27/29] target-sparc: implement sun4v RTC - - - --- 2016-10-01 Artyom Tarasenko New
[26/29] target-sparc: store the UA2005 entries in sun4u format - - - --- 2016-10-01 Artyom Tarasenko New
[25/29] target-sparc: implement UA2005 ASI_MMU (0x21) - - - --- 2016-10-01 Artyom Tarasenko New
[24/29] target-sparc: add more registers to dump_mmu - 1 - --- 2016-10-01 Artyom Tarasenko New
[23/29] target-sparc: implement ST_BLKINIT_ ASIs - - - --- 2016-10-01 Artyom Tarasenko New
[22/29] target-sparc: implement auto-demapping for UA2005 CPUs - - - --- 2016-10-01 Artyom Tarasenko New
[21/29] target-sparc: allow 256M sized pages - - - --- 2016-10-01 Artyom Tarasenko New
[20/29] target-sparc: simplify ultrasparc_tsb_pointer - - - --- 2016-10-01 Artyom Tarasenko New
[19/29] target-sparc: implement UA2005 TSB Pointers - - - --- 2016-10-01 Artyom Tarasenko New
[18/29] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs - - - --- 2016-10-01 Artyom Tarasenko New
[17/29] target-sparc: replace the last tlb entry when no free entries left - - - --- 2016-10-01 Artyom Tarasenko New
[16/29] target-sparc: ignore writes to UA2005 CPU mondo queue register - 1 - --- 2016-10-01 Artyom Tarasenko New
[15/29] target-sparc: allow priveleged ASIs in hyperprivileged mode - - - --- 2016-10-01 Artyom Tarasenko New
[14/29] target-sparc: use direct address translation in hyperprivileged mode - - - --- 2016-10-01 Artyom Tarasenko New
[13/29] target-sparc: fix immediate UA2005 traps - - - --- 2016-10-01 Artyom Tarasenko New
[12/29] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions - 1 - --- 2016-10-01 Artyom Tarasenko New
[11/29] target-sparc: implement UA2005 GL register - - - --- 2016-10-01 Artyom Tarasenko New
[10/29] target-sparc: implement UA2005 hypervisor traps - - - --- 2016-10-01 Artyom Tarasenko New
[09/29] target-sparc: hypervisor mode takes over nucleus mode - - - --- 2016-10-01 Artyom Tarasenko New
[08/29] target-sparc: implement UltraSPARC-T1 Strand status ASR - 1 - --- 2016-10-01 Artyom Tarasenko New
[07/29] target-sparc: implement UA2005 scratchpad registers - - - --- 2016-10-01 Artyom Tarasenko New
[06/29] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE - 1 - --- 2016-10-01 Artyom Tarasenko New
[05/29] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode - 1 - --- 2016-10-01 Artyom Tarasenko New
[04/29] target-sparc: add UltraSPARC T1 TLB #defines - - - --- 2016-10-01 Artyom Tarasenko New
[03/29] target-sparc: add UA2005 TTE bit #defines - - - --- 2016-10-01 Artyom Tarasenko New
[02/29] target-sparc: use explicit mmu register pointers - 1 - --- 2016-10-01 Artyom Tarasenko New
[01/29] target-sparc: don't trap on MMU-fault if MMU is disabled - - - --- 2016-10-01 Artyom Tarasenko New
target-sparc: fix register corruption in ldstub if there is no write permission - 1 1 --- 2016-06-24 Artyom Tarasenko New
[2/2,for-2.6] target-sparc: fix Trap Based Address Register behavior for sparc64 - - - --- 2016-04-14 Artyom Tarasenko New
[1/2,for-2.6] target-sparc: fix Nucleus quad LDD 128 bit access for windowed registers - - - --- 2016-04-14 Artyom Tarasenko New
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