Show patches with: Submitter = Michael Clark       |    State = Action Required       |   450 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v8,05/35] RISC-V: Remove unused class definitions - 1 - --- 2018-04-25 Michael Clark New
[v8,04/35] RISC-V: Remove identity_translate from load_elf - 1 - --- 2018-04-25 Michael Clark New
[v8,03/35] RISC-V: Use ROM base address and size from memmap - 1 - --- 2018-04-25 Michael Clark New
[v8,02/35] RISC-V: Make virt board description match spike - 1 - --- 2018-04-25 Michael Clark New
[v8,01/35] RISC-V: Replace hardcoded constants with enum values - 2 - --- 2018-04-25 Michael Clark New
[PULL,1/1] RISC-V: Workaround for critical mstatus.FS bug - 1 1 --- 2018-03-29 Michael Clark New
[PULL,2/2] RISC-V: Fix incorrect disassembly for addiw - 2 - --- 2018-03-28 Michael Clark New
[PULL,1/2] RISC-V: Convert cpu definition to future model - 2 - --- 2018-03-28 Michael Clark New
[v2,1/1] RISC-V: Workaround for critical mstatus.FS bug - - 1 --- 2018-03-28 Michael Clark New
[v2,1/1] RISC-V: Workaround for critical mstatus.FS MTTCG bug - 1 1 --- 2018-03-28 Michael Clark New
[v1,2/2] RISC-V: Fix incorrect disassembly for addiw - 2 - --- 2018-03-27 Michael Clark New
[v1,1/2] RISC-V: Convert cpu definition to future model - 3 - --- 2018-03-27 Michael Clark New
[v1,1/1] RISC-V: Workaround for critical mstatus.FS MTTCG bug - 1 1 --- 2018-03-27 Michael Clark New
[v1] RISC-V: RISC-V TCG backend work in progress - - - --- 2018-03-24 Michael Clark New
[v6,26/26] RISC-V: Workaround for critical mstatus.FS MTTCG bug - - - --- 2018-03-24 Michael Clark New
[v6,25/26] RISC-V: Fix incorrect disassembly for addiw - - - --- 2018-03-24 Michael Clark New
[v6,24/26] RISC-V: Remove erroneous comment from translate.c - - - --- 2018-03-24 Michael Clark New
[v6,23/26] RISC-V: Clear mtval/stval on exceptions without info - - - --- 2018-03-24 Michael Clark New
[v6,21/26] RISC-V: Remove support for adhoc X_COP interrupt - - - --- 2018-03-24 Michael Clark New
[v6,20/26] RISC-V: No traps on writes to misa, minstret, mcycle - - - --- 2018-03-24 Michael Clark New
[v6,19/26] RISC-V: vectored traps are optional - - - --- 2018-03-24 Michael Clark New
[v6,18/26] RISC-V: riscv-qemu port supports sv39 and sv48 - - - --- 2018-03-24 Michael Clark New
[v6,16/26] RISC-V: Hardwire satp to 0 for no-mmu case - - - --- 2018-03-24 Michael Clark New
[v6,14/26] RISC-V: Use memory_region_is_ram in pte update - - - --- 2018-03-24 Michael Clark New
[v6,11/26] RISC-V: Update E order and I extension order - - - --- 2018-03-24 Michael Clark New
[v6,10/26] RISC-V: Improve page table walker spec compliance - - - --- 2018-03-24 Michael Clark New
[v6,08/26] RISC-V: Make sure rom has space for fdt - - - --- 2018-03-24 Michael Clark New
[v6,06/26] RISC-V: Mark ROM read-only after copying in code - - - --- 2018-03-24 Michael Clark New
[PULL,24/24] RISC-V: Remove erroneous comment from translate.c - - - --- 2018-03-21 Michael Clark New
[PULL,23/24] RISC-V: Clear mtval/stval on exceptions without info - - - --- 2018-03-21 Michael Clark New
[PULL,22/24] RISC-V: Convert cpu definition towards future model - 2 - --- 2018-03-21 Michael Clark New
[PULL,21/24] RISC-V: Remove support for adhoc X_COP interrupt - - - --- 2018-03-21 Michael Clark New
[PULL,20/24] RISC-V: No traps on writes to misa, minstret, mcycle - - - --- 2018-03-21 Michael Clark New
[PULL,19/24] RISC-V: vectored traps are optional - - - --- 2018-03-21 Michael Clark New
[PULL,18/24] RISC-V: riscv-qemu port supports sv39 and sv48 - - - --- 2018-03-21 Michael Clark New
[PULL,17/24] RISC-V: Remove braces from satp case statement - 1 - --- 2018-03-21 Michael Clark New
[PULL,16/24] RISC-V: Hardwire satp to 0 for no-mmu case - - - --- 2018-03-21 Michael Clark New
[PULL,15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection - 1 - --- 2018-03-21 Michael Clark New
[PULL,14/24] RISC-V: Use memory_region_is_ram in pte update - - - --- 2018-03-21 Michael Clark New
[PULL,13/24] RISC-V: Make virt header comment title consistent - 1 - --- 2018-03-21 Michael Clark New
[PULL,12/24] RISC-V: Make some header guards more specific - 1 - --- 2018-03-21 Michael Clark New
[PULL,11/24] RISC-V: Update E order and I extension order - - - --- 2018-03-21 Michael Clark New
[PULL,10/24] RISC-V: Improve page table walker spec compliance - - - --- 2018-03-21 Michael Clark New
[PULL,09/24] RISC-V: Include intruction hex in disassembly - 1 - --- 2018-03-21 Michael Clark New
[PULL,08/24] RISC-V: Make sure rom has space for fdt - - - --- 2018-03-21 Michael Clark New
[PULL,07/24] RISC-V: Remove unused class definitions - 1 - --- 2018-03-21 Michael Clark New
[PULL,06/24] RISC-V: Mark ROM read-only after copying in code - - - --- 2018-03-21 Michael Clark New
[PULL,05/24] RISC-V: Remove identity_translate from load_elf - 1 - --- 2018-03-21 Michael Clark New
[PULL,04/24] RISC-V: Use ROM base address and size from memmap - 1 - --- 2018-03-21 Michael Clark New
[PULL,03/24] RISC-V: Make virt board description match spike - 1 - --- 2018-03-21 Michael Clark New
[PULL,02/24] RISC-V: Replace hardcoded constants with enum values - 1 - --- 2018-03-21 Michael Clark New
[PULL,01/24] RISC-V: Make virt create_fdt interface consistent - 1 - --- 2018-03-21 Michael Clark New
[v4,26/26] RISC-V: Fix riscv_isa_string memory size bug - 1 - --- 2018-03-19 Michael Clark New
[v4,25/26] RISC-V: Remove erroneous comment from translate.c - - - --- 2018-03-19 Michael Clark New
[v4,24/26] RISC-V: Clear mtval/stval on exceptions without info - - - --- 2018-03-19 Michael Clark New
[v4,23/26] RISC-V: Convert cpu definition towards future model - 1 - --- 2018-03-19 Michael Clark New
[v4,22/26] RISC-V: Remove support for adhoc X_COP interrupt - - - --- 2018-03-19 Michael Clark New
[v4,21/26] RISC-V: No traps on writes to misa, minstret, mcycle - - - --- 2018-03-19 Michael Clark New
[v4,20/26] RISC-V: vectored traps are optional - - - --- 2018-03-19 Michael Clark New
[v4,19/26] RISC-V: riscv-qemu port supports sv39 and sv48 - - - --- 2018-03-19 Michael Clark New
[v4,18/26] RISC-V: Remove braces from satp case statement - 1 - --- 2018-03-19 Michael Clark New
[v4,17/26] RISC-V: Hardwire satp to 0 for no-mmu case - - - --- 2018-03-19 Michael Clark New
[v4,16/26] RISC-V: Remove EM_RISCV ELF_MACHINE indirection - 1 - --- 2018-03-19 Michael Clark New
[v4,15/26] RISC-V: Use memory_region_is_ram in pte update - - - --- 2018-03-19 Michael Clark New
[v4,14/26] RISC-V: Make virt header comment title consistent - 1 - --- 2018-03-19 Michael Clark New
[v4,13/26] RISC-V: Make some header guards more specific - 1 - --- 2018-03-19 Michael Clark New
[v4,12/26] RISC-V: Update E order and I extension order - - - --- 2018-03-19 Michael Clark New
[v4,11/26] RISC-V: Improve page table walker spec compliance - - - --- 2018-03-19 Michael Clark New
[v4,10/26] RISC-V: Hold rcu_read_lock when accessing memory - - - --- 2018-03-19 Michael Clark New
[v4,09/26] RISC-V: Include intruction hex in disassembly - 1 - --- 2018-03-19 Michael Clark New
[v4,08/26] RISC-V: Make sure rom has space for fdt - - - --- 2018-03-19 Michael Clark New
[v4,07/26] RISC-V: Remove unused class definitions - 1 - --- 2018-03-19 Michael Clark New
[v4,06/26] RISC-V: Mark ROM read-only after copying in code - - - --- 2018-03-19 Michael Clark New
[v4,05/26] RISC-V: Remove identity_translate from load_elf - 1 - --- 2018-03-19 Michael Clark New
[v4,04/26] RISC-V: Use ROM base address and size from memmap - 1 - --- 2018-03-19 Michael Clark New
[v4,03/26] RISC-V: Make virt board description match spike - 1 - --- 2018-03-19 Michael Clark New
[v4,02/26] RISC-V: Replace hardcoded constants with enum values - 1 - --- 2018-03-19 Michael Clark New
[v4,01/26] RISC-V: Make virt create_fdt interface consistent - 1 - --- 2018-03-19 Michael Clark New
[v3,24/24] RISC-V: Clear mtval/stval on exceptions without info - - - --- 2018-03-16 Michael Clark New
[v3,23/24] RISC-V: Convert cpu definition towards future model - 2 - --- 2018-03-16 Michael Clark New
[v3,22/24] RISC-V: Remove support for adhoc X_COP interrupt - - - --- 2018-03-16 Michael Clark New
[v3,21/24] RISC-V: No traps on writes to misa, minstret, mcycle - - - --- 2018-03-16 Michael Clark New
[v3,20/24] RISC-V: vectored traps are optional - - - --- 2018-03-16 Michael Clark New
[v3,19/24] RISC-V: riscv-qemu port supports sv39 and sv48 - - - --- 2018-03-16 Michael Clark New
[v3,18/24] RISC-V: Remove braces from satp case statement - 1 - --- 2018-03-16 Michael Clark New
[v3,17/24] RISC-V: Hardwire satp to 0 for no-mmu case - - - --- 2018-03-16 Michael Clark New
[v3,16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection - 1 - --- 2018-03-16 Michael Clark New
[v3,15/24] RISC-V: Use memory_region_is_ram in pte update - - - --- 2018-03-16 Michael Clark New
[v3,14/24] RISC-V: Make virt header comment title consistent - 1 - --- 2018-03-16 Michael Clark New
[v3,13/24] RISC-V: Make some header guards more specific - 1 - --- 2018-03-16 Michael Clark New
[v3,12/24] RISC-V: Update E order and I extension order - - - --- 2018-03-16 Michael Clark New
[v3,11/24] RISC-V: Improve page table walker spec compliance - - - --- 2018-03-16 Michael Clark New
[v3,10/24] RISC-V: Hold rcu_read_lock when accessing memory - - - --- 2018-03-16 Michael Clark New
[v3,09/24] RISC-V: Include intruction hex in disassembly - 1 - --- 2018-03-16 Michael Clark New
[v3,08/24] RISC-V: Make sure rom has space for fdt - - - --- 2018-03-16 Michael Clark New
[v3,07/24] RISC-V: Remove unused class definitions - 1 - --- 2018-03-16 Michael Clark New
[v3,06/24] RISC-V: Mark ROM read-only after copying in code - - - --- 2018-03-16 Michael Clark New
[v3,05/24] RISC-V: Remove identity_translate from load_elf - 1 - --- 2018-03-16 Michael Clark New
[v3,04/24] RISC-V: Use ROM base address and size from memmap - 1 - --- 2018-03-16 Michael Clark New
[v3,03/24] RISC-V: Make virt board description match spike - 1 - --- 2018-03-16 Michael Clark New
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