Show patches with: Submitter = Michael Clark       |    State = Action Required       |   450 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,02/24] RISC-V: Replace hardcoded constants with enum values - 1 - --- 2018-03-16 Michael Clark New
[v3,01/24] RISC-V: Make virt create_fdt interface consistent - 1 - --- 2018-03-16 Michael Clark New
[v3] RISC-V: Fix riscv_isa_string memory size bug - 2 - --- 2018-03-16 Michael Clark New
[v2] RISC-V: Fix riscv_isa_string, use popcount to count bits - - - --- 2018-03-09 Michael Clark New
RISC-V: Fix isa string logic bug, use popcount to count bits - - - --- 2018-03-09 Michael Clark New
[v2,23/23] RISC-V: Convert cpu definition towards future model - 1 - --- 2018-03-09 Michael Clark New
[v2,22/23] RISC-V: Remove support for adhoc X_COP interrupt - - - --- 2018-03-09 Michael Clark New
[v2,21/23] RISC-V: No traps on writes to misa, minstret, mcycle - - - --- 2018-03-09 Michael Clark New
[v2,20/23] RISC-V: vectored traps are optional - - - --- 2018-03-09 Michael Clark New
[v2,19/23] RISC-V: riscv-qemu port supports sv39 and sv48 - - - --- 2018-03-09 Michael Clark New
[v2,18/23] RISC-V: Remove braces from satp case statement - 1 - --- 2018-03-09 Michael Clark New
[v2,17/23] RISC-V: Hardwire satp to 0 for no-mmu case - - - --- 2018-03-09 Michael Clark New
[v2,16/23] RISC-V: Remove EM_RISCV ELF_MACHINE indirection - 1 - --- 2018-03-09 Michael Clark New
[v2,15/23] RISC-V: Use memory_region_is_ram in pte update - 1 - --- 2018-03-09 Michael Clark New
[v2,14/23] RISC-V: Make virt header comment title consistent - 1 - --- 2018-03-09 Michael Clark New
[v2,13/23] RISC-V: Make some header guards more specific - 1 - --- 2018-03-09 Michael Clark New
[v2,12/23] RISC-V: Update E order and I extension order - - - --- 2018-03-09 Michael Clark New
[v2,11/23] RISC-V: Improve page table walker spec compliance - - - --- 2018-03-09 Michael Clark New
[v2,10/23] RISC-V: Hold rcu_read_lock when accessing memory - - - --- 2018-03-09 Michael Clark New
[v2,09/23] RISC-V: Include intruction hex in disassembly - 1 - --- 2018-03-09 Michael Clark New
[v2,08/23] RISC-V: Make sure rom has space for fdt - - - --- 2018-03-09 Michael Clark New
[v2,07/23] RISC-V: Remove unused class definitions - 1 - --- 2018-03-09 Michael Clark New
[v2,06/23] RISC-V: Mark ROM read-only after copying in code - - - --- 2018-03-09 Michael Clark New
[v2,05/23] RISC-V: Remove identity_translate from load_elf - 1 - --- 2018-03-09 Michael Clark New
[v2,04/23] RISC-V: Use ROM base address and size from memmap - 1 - --- 2018-03-09 Michael Clark New
[v2,03/23] RISC-V: Make virt board description match spike - 1 - --- 2018-03-09 Michael Clark New
[v2,02/23] RISC-V: Replace hardcoded constants with enum values - 1 - --- 2018-03-09 Michael Clark New
[v2,01/23] RISC-V: Make virt create_fdt interface consistent - 1 - --- 2018-03-09 Michael Clark New
[v1] RISC-V: Convert cpu definition towards future model - - - --- 2018-03-07 Michael Clark New
[v1,22/22] RISC-V: Remove support for adhoc X_COP interrupt - - - --- 2018-03-06 Michael Clark New
[v1,21/22] RISC-V: No traps on writes to misa/minstret/mcycle - - - --- 2018-03-06 Michael Clark New
[v1,20/22] RISC-V: vectored traps are optional - - - --- 2018-03-06 Michael Clark New
[v1,19/22] RISC-V: riscv-qemu port supports sv39 and sv48 - - - --- 2018-03-06 Michael Clark New
[v1,18/22] RISC-V: Remove braces from satp case statement - - - --- 2018-03-06 Michael Clark New
[v1,17/22] RISC-V: Hardwire satp to 0 for no-mmu case - - - --- 2018-03-06 Michael Clark New
[v1,16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection - - - --- 2018-03-06 Michael Clark New
[v1,15/22] RISC-V: Use memory_region_is_ram in pte update - - - --- 2018-03-06 Michael Clark New
[v1,14/22] RISC-V: Make virt header comment title consistent - - - --- 2018-03-06 Michael Clark New
[v1,13/22] RISC-V: Make some header guards more specific - - - --- 2018-03-06 Michael Clark New
[v1,12/22] RISC-V: Update E order and I extension order - - - --- 2018-03-06 Michael Clark New
[v1,11/22] RISC-V: Improve page table walker spec compliance - - - --- 2018-03-06 Michael Clark New
[v1,10/22] RISC-V: Hold rcu_read_lock when accessing memory - - - --- 2018-03-06 Michael Clark New
[v1,09/22] RISC-V: Include hexidecimal in disassembly - - - --- 2018-03-06 Michael Clark New
[v1,08/22] RISC-V: Make sure rom has space for fdt - - - --- 2018-03-06 Michael Clark New
[v1,07/22] RISC-V: Remove unused class definitions - - - --- 2018-03-06 Michael Clark New
[v1,06/22] RISC-V: Mark ROM read-only after copying in code - - - --- 2018-03-06 Michael Clark New
[v1,05/22] RISC-V: Remove identity_translate from load_elf - - - --- 2018-03-06 Michael Clark New
[v1,04/22] RISC-V: Use ROM base address and size from memmap - - - --- 2018-03-06 Michael Clark New
[v1,03/22] RISC-V: Make virt board description match spike - - - --- 2018-03-06 Michael Clark New
[v1,02/22] RISC-V: Replace hardcoded constants with enum values - - - --- 2018-03-06 Michael Clark New
[v1,20/22] RISC-V: vectored traps are optional - - - --- 2018-03-06 Michael Clark New
[v1,19/22] RISC-V: riscv-qemu port supports sv39 and sv48 - - - --- 2018-03-06 Michael Clark New
[v1,18/22] RISC-V: Remove braces from satp case statement with - 1 - --- 2018-03-06 Michael Clark New
[v1,17/22] RISC-V: Ingore satp writes and return 0 for reads - - - --- 2018-03-06 Michael Clark New
[v1,16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection from - - - --- 2018-03-06 Michael Clark New
[v1,15/22] RISC-V: Use memory_region_is_ram in atomic pte - - - --- 2018-03-06 Michael Clark New
[v1,14/22] RISC-V: Make virt header comment title consistent - - - --- 2018-03-06 Michael Clark New
[v1,13/22] RISC-V: Make spike and virt header guards more - - - --- 2018-03-06 Michael Clark New
[v1,12/22] RISC-V: Update E order and I extension order - - - --- 2018-03-06 Michael Clark New
[v1,11/22] RISC-V: Improve page table walker spec compliance - - - --- 2018-03-06 Michael Clark New
[v1,10/22] RISC-V: Hold rcu_read_lock when accessing memory - - - --- 2018-03-06 Michael Clark New
[v1,09/22] RISC-V: Include hexidecimal instruction in - 1 - --- 2018-03-06 Michael Clark New
[v1,08/22] RISC-V: Make sure the emulated rom has space for - - - --- 2018-03-06 Michael Clark New
[v1,07/22] RISC-V: Remove unused class definitions from - - - --- 2018-03-06 Michael Clark New
[v1,06/22] RISC-V: Mark ROM read-only after copying in code and - - - --- 2018-03-06 Michael Clark New
[v1,05/22] RISC-V: Remove redundant identity_translate from - 1 - --- 2018-03-06 Michael Clark New
[v1,04/22] RISC-V: Use ROM base address and size from memory - - - --- 2018-03-06 Michael Clark New
[v1,03/22] RISC-V: Make virt board description match spike - - - --- 2018-03-06 Michael Clark New
[v1,02/22] RISC-V: Replace hardcoded constants with enum values - 1 - --- 2018-03-06 Michael Clark New
[v1,01/22] RISC-V: Make virt create_fdt interface consistent - - - --- 2018-03-06 Michael Clark New
[v8,23/23] RISC-V Build Infrastructure - 2 - --- 2018-03-02 Michael Clark New
[v8,22/23] SiFive Freedom U Series RISC-V Machine 1 - - --- 2018-03-02 Michael Clark New
[v8,21/23] SiFive Freedom E Series RISC-V Machine 1 - - --- 2018-03-02 Michael Clark New
[v8,20/23] SiFive RISC-V PRCI Block 1 - - --- 2018-03-02 Michael Clark New
[v8,19/23] SiFive RISC-V UART Device 1 1 - --- 2018-03-02 Michael Clark New
[v8,18/23] RISC-V VirtIO Machine 1 - - --- 2018-03-02 Michael Clark New
[v8,17/23] SiFive RISC-V Test Finisher 1 1 - --- 2018-03-02 Michael Clark New
[v8,16/23] RISC-V Spike Machines 1 - - --- 2018-03-02 Michael Clark New
[v8,15/23] SiFive RISC-V PLIC Block 1 - - --- 2018-03-02 Michael Clark New
[v8,14/23] SiFive RISC-V CLINT Block 1 - - --- 2018-03-02 Michael Clark New
[v8,13/23] RISC-V HART Array - 2 - --- 2018-03-02 Michael Clark New
[v8,12/23] RISC-V HTIF Console - 2 - --- 2018-03-02 Michael Clark New
[v8,11/23] Add symbol table callback interface to load_elf - 2 - --- 2018-03-02 Michael Clark New
[v8,10/23] RISC-V Linux User Emulation - 1 - --- 2018-03-02 Michael Clark New
[v8,09/23] RISC-V Physical Memory Protection - 1 - --- 2018-03-02 Michael Clark New
[v8,08/23] RISC-V TCG Code Generation - 1 - --- 2018-03-02 Michael Clark New
[v8,07/23] RISC-V GDB Stub - 2 - --- 2018-03-02 Michael Clark New
[v8,06/23] RISC-V FPU Support - 1 - --- 2018-03-02 Michael Clark New
[v8,05/23] RISC-V CPU Helpers - 1 - --- 2018-03-02 Michael Clark New
[v8,04/23] RISC-V Disassembler - 1 - --- 2018-03-02 Michael Clark New
[v8,03/23] RISC-V CPU Core Definition - 1 - --- 2018-03-02 Michael Clark New
[v8,02/23] RISC-V ELF Machine Definition - 3 - --- 2018-03-02 Michael Clark New
[v8,01/23] RISC-V Maintainers - 2 - --- 2018-03-02 Michael Clark New
[v7,23/23] RISC-V Build Infrastructure - 1 - --- 2018-02-26 Michael Clark New
[v7,22/23] SiFive Freedom U500 RISC-V Machine 1 - - --- 2018-02-26 Michael Clark New
[v7,21/23] SiFive Freedom E300 RISC-V Machine 1 - - --- 2018-02-26 Michael Clark New
[v7,20/23] SiFive RISC-V PRCI Block 1 - - --- 2018-02-26 Michael Clark New
[v7,19/23] SiFive RISC-V UART Device 1 - - --- 2018-02-26 Michael Clark New
[v7,18/23] RISC-V VirtIO Machine 1 - - --- 2018-02-26 Michael Clark New
[v7,17/23] SiFive RISC-V Test Finisher 1 - - --- 2018-02-26 Michael Clark New
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