Show patches with: Submitter = LIU Zhiwei       |    State = Action Required       |   1061 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,21/37] target/riscv: 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,19/37] target/riscv: Partial-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,14/37] target/riscv: 16-bit Packing Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,13/37] target/riscv: 8-bit Unpacking Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,10/37] target/riscv: SIMD 8-bit Multiply Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,09/37] target/riscv: SIMD 16-bit Multiply Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-24 LIU Zhiwei New
[v3,08/37] target/riscv: SIMD 8-bit Compare Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,07/37] target/riscv: SIMD 16-bit Compare Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-24 LIU Zhiwei New
[v3,06/37] target/riscv: SIMD 8-bit Shift Instructions target/riscv: support packed extension v0.9.4 1 1 - --- 2021-06-24 LIU Zhiwei New
[v3,05/37] target/riscv: SIMD 16-bit Shift Instructions target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,04/37] target/riscv: 8-bit Addition & Subtraction Instruction target/riscv: support packed extension v0.9.4 1 1 - --- 2021-06-24 LIU Zhiwei New
[v3,03/37] target/riscv: 16-bit Addition & Subtraction Instructions target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,02/37] target/riscv: Make the vector helper functions public target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,01/37] target/riscv: implementation-defined constant parameters target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-24 LIU Zhiwei New
[5/5] tcg: Implement tcg_gen_vec_add{sub}32_tl tcg: Add 32-bit vector operations - - - --- 2021-06-24 LIU Zhiwei New
[4/5] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32 tcg: Add 32-bit vector operations - - - --- 2021-06-24 LIU Zhiwei New
[3/5] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 tcg: Add 32-bit vector operations - - - --- 2021-06-24 LIU Zhiwei New
[2/5] tcg: Add tcg_gen_vec_add{sub}8_i32 tcg: Add 32-bit vector operations - - - --- 2021-06-24 LIU Zhiwei New
[1/5] tcg: Add tcg_gen_vec_add{sub}16_i32 tcg: Add 32-bit vector operations - - - --- 2021-06-24 LIU Zhiwei New
[v2,37/37] target/riscv: configure and turn on packed extension from command line target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,36/37] target/riscv: RV64 Only 32-bit Packing Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,32/37] target/riscv: RV64 Only 32-bit Multiply Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,27/37] target/riscv: Non-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,26/37] target/riscv: 32-bit Computation Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,21/37] target/riscv: 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,19/37] target/riscv: Partial-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,14/37] target/riscv: 16-bit Packing Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,13/37] target/riscv: 8-bit Unpacking Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,10/37] target/riscv: SIMD 8-bit Multiply Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,09/37] target/riscv: SIMD 16-bit Multiply Instructions target/riscv: support packed extension v0.9.4 - - - --- 2021-06-10 LIU Zhiwei New
[v2,08/37] target/riscv: SIMD 8-bit Compare Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,07/37] target/riscv: SIMD 16-bit Compare Instructions target/riscv: support packed extension v0.9.4 1 - - --- 2021-06-10 LIU Zhiwei New
[v2,06/37] target/riscv: SIMD 8-bit Shift Instructions target/riscv: support packed extension v0.9.4 1 1 - --- 2021-06-10 LIU Zhiwei New
[v2,05/37] target/riscv: SIMD 16-bit Shift Instructions target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-10 LIU Zhiwei New
[v2,04/37] target/riscv: 8-bit Addition & Subtraction Instruction target/riscv: support packed extension v0.9.4 1 1 - --- 2021-06-10 LIU Zhiwei New
[v2,03/37] target/riscv: 16-bit Addition & Subtraction Instructions target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-10 LIU Zhiwei New
[v2,02/37] target/riscv: Make the vector helper functions public target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-10 LIU Zhiwei New
[v2,01/37] target/riscv: implementation-defined constant parameters target/riscv: support packed extension v0.9.4 - 1 - --- 2021-06-10 LIU Zhiwei New
[1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode [1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode - - - --- 2021-05-27 LIU Zhiwei New
target/riscv: Pass the same value to oprsz and maxsz. target/riscv: Pass the same value to oprsz and maxsz. - 1 - --- 2021-05-21 LIU Zhiwei New
[RFC,11/11] target/riscv: Update interrupt return in CLIC mode RISC-V: support clic v0.9 specification - - - --- 2021-04-09 LIU Zhiwei New
[RFC,10/11] target/riscv: Update interrupt handling in CLIC mode RISC-V: support clic v0.9 specification - - - --- 2021-04-09 LIU Zhiwei New
[RFC,09/11] target/riscv: Update CSR mclicbase in CLIC mode RISC-V: support clic v0.9 specification - 1 - --- 2021-04-09 LIU Zhiwei New
[RFC,08/11] target/riscv: Update CSR xnxti in CLIC mode RISC-V: support clic v0.9 specification - - - --- 2021-04-09 LIU Zhiwei New
[RFC,07/11] target/riscv: Update CSR xtvt in CLIC mode RISC-V: support clic v0.9 specification - - - --- 2021-04-09 LIU Zhiwei New
[RFC,06/11] target/riscv: Update CSR xtvec in CLIC mode RISC-V: support clic v0.9 specification - - - --- 2021-04-09 LIU Zhiwei New
[RFC,05/11] target/riscv: Update CSR xip in CLIC mode RISC-V: support clic v0.9 specification - 1 - --- 2021-04-09 LIU Zhiwei New
[RFC,04/11] target/riscv: Update CSR xie in CLIC mode RISC-V: support clic v0.9 specification - 1 - --- 2021-04-09 LIU Zhiwei New
[RFC,03/11] hw/intc: Add CLIC device RISC-V: support clic v0.9 specification - - - --- 2021-04-09 LIU Zhiwei New
[RFC,02/11] target/riscv: Update CSR xintthresh in CLIC mode RISC-V: support clic v0.9 specification - 1 - --- 2021-04-09 LIU Zhiwei New
[RFC,01/11] target/riscv: Add CLIC CSR mintstatus RISC-V: support clic v0.9 specification - - - --- 2021-04-09 LIU Zhiwei New
[38/38] target/riscv: configure and turn on packed extension from command line target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[37/38] target/riscv: RV64 Only 32-bit Packing Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[33/38] target/riscv: RV64 Only 32-bit Multiply Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[28/38] target/riscv: Non-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[27/38] target/riscv: 32-bit Computation Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[22/38] target/riscv: 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[20/38] target/riscv: Partial-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
[19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - --- 2021-02-12 LIU Zhiwei New
[17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions target/riscv: support packed extension v0.9.2 1 - - --- 2021-02-12 LIU Zhiwei New
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