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: Submitter =
Alistair Francis
| 937 patches
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Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
[v5,1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0
Initial support for SPDM Responders
- 1 -
-
-
-
2024-03-07
Alistair Francis
New
[v4,3/3] hw/nvme: Add SPDM over DOE support
Initial support for SPDM Responders
1 1 -
-
-
-
2024-02-13
Alistair Francis
New
[v4,2/3] backends: Initial support for SPDM socket support
Initial support for SPDM Responders
- - -
-
-
-
2024-02-13
Alistair Francis
New
[v4,1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0
Initial support for SPDM Responders
- 1 -
-
-
-
2024-02-13
Alistair Francis
New
[PULL,61/61] target/riscv: add rv32i, rv32e and rv64e CPUs
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,60/61] target/riscv/cpu.c: add riscv_bare_cpu_init()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,59/61] target/riscv: Enable xtheadsync under user mode
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
1 - -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,58/61] qemu-options: enable -smbios option on RISC-V
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
1 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,57/61] target/riscv: SMBIOS support for RISC-V virt machine
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,56/61] smbios: function to set default processor family
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,55/61] smbios: add processor-family option
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,54/61] target/riscv: support new isa extension detection devicetree properties
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 3 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,53/61] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,52/61] target/riscv: Expose Zaamo and Zalrsc extensions
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,51/61] target/riscv: Check 'A' and split extensions for atomic instructions
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,50/61] target/riscv: Add Zaamo and Zalrsc extension infrastructure
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,49/61] hw/riscv/virt.c: use g_autofree in create_fdt_*
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,48/61] hw/riscv/virt.c: use g_autofree in virt_machine_init()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,47/61] hw/riscv/virt.c: use g_autofree in create_fdt_virtio()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,46/61] hw/riscv/virt.c: use g_autofree in create_fdt_sockets()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,45/61] hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,44/61] hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,43/61] hw/riscv/virt-acpi-build.c: fix leak in build_rhct()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,42/61] target/riscv: Use RISCVException as return type for all csr ops
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,41/61] target/riscv: FCSR doesn't contain vxrm and vxsat
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,40/61] target/riscv: Validate misa_mxl_max only once
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,39/61] target/riscv: Move misa_mxl_max to class
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,38/61] target/riscv: Remove misa_mxl validation
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
2 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,37/61] target/riscv/kvm: get/set vector vregs[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
1 - -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,36/61] target/riscv/kvm: initialize 'vlenb' via get-reg-list
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
1 - -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,35/61] target/riscv/kvm: change kvm_reg_id to uint64_t
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,34/61] target/riscv/cpu.c: remove cpu->cfg.vlen
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,33/61] trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,32/61] target/riscv: change vext_get_vlmax() arguments
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,31/61] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,30/61] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,29/61] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,28/61] target/riscv/vector_helper.c: use 'vlenb'
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,27/61] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,26/61] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,25/61] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,24/61] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,23/61] target/riscv/csr.c: use 'vlenb' instead of 'vlen'
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,22/61] target/riscv: add 'vlenb' field in cpu->cfg
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,21/61] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,20/61] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,19/61] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,18/61] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,17/61] target/riscv: remove riscv_cpu_options[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,16/61] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,15/61] target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,14/61] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,13/61] target/riscv: create finalize_features() for KVM
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,12/61] target/riscv: move 'elen' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,11/61] target/riscv: move 'vlen' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,10/61] target/riscv: rework 'vext_spec'
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,09/61] target/riscv: rework 'priv_spec'
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,08/61] target/riscv: move 'pmp' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,07/61] target/riscv: move 'mmu' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,06/61] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,05/61] target/riscv: make riscv_cpu_is_vendor() public
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,04/61] target/riscv/cpu_cfg.h: remove unused fields
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 1 1
-
-
-
2024-02-09
Alistair Francis
New
[PULL,03/61] target/riscv: Add step to validate 'B' extension
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 3 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,02/61] target/riscv: Add infrastructure for 'B' MISA extension
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 3 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions
- 2 -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,00/61] riscv-to-apply queue
- - -
-
-
-
2024-02-09
Alistair Francis
New
[PULL,65/65] target/riscv: Ensure mideleg is set correctly on reset
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,64/65] target/riscv: Don't adjust vscause for exceptions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,63/65] target/riscv: Assert that the CSR numbers will be correct
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 1 -
-
-
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2024-01-10
Alistair Francis
New
[PULL,60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,59/65] target/riscv/kvm: add RVV and Vector CSR regs
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,57/65] linux-headers: riscv: add ptrace.h
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,56/65] linux-headers: Update to Linux v6.7-rc5
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,54/65] target/riscv: add rva22s64 cpu
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,53/65] target/riscv: add RVA22S64 profile
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,52/65] target/riscv: add 'parent' in profile description
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,51/65] target/riscv: add satp_mode profile support
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,49/65] target/riscv/cpu.c: finalize satp_mode earlier
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,48/65] target/riscv: add priv ver restriction to profiles
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,47/65] target/riscv: implement svade
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,46/65] target/riscv: add 'rva22u64' CPU
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,44/65] target/riscv/tcg: validate profiles during finalize
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,43/65] target/riscv/tcg: honor user choice for G MISA bits
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,42/65] target/riscv/tcg: add hash table insert helpers
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,41/65] target/riscv/tcg: handle profile MISA bits
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,39/65] target/riscv/tcg: add MISA user options hash
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,38/65] target/riscv/tcg: add user flag for profile support
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,36/65] target/riscv: add rva22u64 profile definition
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,34/65] target/riscv/tcg: add 'zic64b' support
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,33/65] target/riscv: add zicbop extension flag
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
[PULL,32/65] target/riscv: add rv64i CPU
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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2024-01-10
Alistair Francis
New
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