Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,1/9] target/riscv: Remove the hardcoded RVXLEN macro RISC-V: Steps towards running 32-bit guests on - 2 - --- 2021-04-13 Alistair Francis New
[v3,8/8] target/riscv: Add ePMP support for the Ibex CPU RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-13 Alistair Francis New
[v3,7/8] target/riscv/pmp: Remove outdated comment RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-13 Alistair Francis New
[v3,6/8] target/riscv: Add a config option for ePMP RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-13 Alistair Francis New
[v3,5/8] target/riscv: Implementation of enhanced PMP (ePMP) RISC-V: Add support for ePMP v0.9.1 - - - --- 2021-04-13 Alistair Francis New
[v3,4/8] target/riscv: Add ePMP CSR access functions RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-13 Alistair Francis New
[v3,3/8] target/riscv: Add the ePMP feature RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-13 Alistair Francis New
[v3,2/8] target/riscv: Define ePMP mseccfg RISC-V: Add support for ePMP v0.9.1 - 2 - --- 2021-04-13 Alistair Francis New
[v3,1/8] target/riscv: Fix the PMP is locked check when using TOR RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-13 Alistair Francis New
[v2,8/8] target/riscv: Add ePMP support for the Ibex CPU RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-09 Alistair Francis New
[v2,7/8] target/riscv/pmp: Remove outdated comment RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-09 Alistair Francis New
[v2,6/8] target/riscv: Add a config option for ePMP RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-09 Alistair Francis New
[v2,5/8] target/riscv: Implementation of enhanced PMP (ePMP) RISC-V: Add support for ePMP v0.9.1 - - - --- 2021-04-09 Alistair Francis New
[v2,4/8] target/riscv: Add ePMP CSR access functions RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-09 Alistair Francis New
[v2,3/8] target/riscv: Add the ePMP feature RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-09 Alistair Francis New
[v2,2/8] target/riscv: Define ePMP mseccfg RISC-V: Add support for ePMP v0.9.1 - 2 - --- 2021-04-09 Alistair Francis New
[v2,1/8] target/riscv: Fix the PMP is locked check when using TOR RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-09 Alistair Francis New
[v1,1/1] MAINTAINERS: Update the RISC-V CPU Maintainers [v1,1/1] MAINTAINERS: Update the RISC-V CPU Maintainers 2 1 - --- 2021-04-06 Alistair Francis New
[v1,8/8] target/riscv: Include RV32 instructions in RV64 build RISC-V: Steps towards running 32-bit guests on - - - --- 2021-04-02 Alistair Francis New
[v1,7/8] target/riscv: Remove an unused CASE_OP_32_64 macro RISC-V: Steps towards running 32-bit guests on - 2 - --- 2021-04-02 Alistair Francis New
[v1,6/8] target/riscv: Remove the unused HSTATUS_WPRI macro RISC-V: Steps towards running 32-bit guests on - 2 - --- 2021-04-02 Alistair Francis New
[v1,5/8] target/riscv: Remove the hardcoded SATP_MODE macro RISC-V: Steps towards running 32-bit guests on - - - --- 2021-04-02 Alistair Francis New
[v1,4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - - - --- 2021-04-02 Alistair Francis New
[v1,3/8] target/riscv: Remove the hardcoded HGATP_MODE macro RISC-V: Steps towards running 32-bit guests on - 1 - --- 2021-04-02 Alistair Francis New
[v1,2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - 2 - --- 2021-04-02 Alistair Francis New
[v1,1/8] target/riscv: Remove the hardcoded RVXLEN macro RISC-V: Steps towards running 32-bit guests on - 2 - --- 2021-04-02 Alistair Francis New
[v1,8/8] target/riscv: Add ePMP support for the Ibex CPU RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-02 Alistair Francis New
[v1,7/8] target/riscv/pmp: Remove outdated comment RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-02 Alistair Francis New
[v1,6/8] target/riscv: Add a config option for ePMP RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-02 Alistair Francis New
[v1,5/8] target/riscv: Implementation of enhanced PMP (ePMP) RISC-V: Add support for ePMP v0.9.1 - - - --- 2021-04-02 Alistair Francis New
[v1,4/8] target/riscv: Add ePMP CSR access functions RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-02 Alistair Francis New
[v1,3/8] target/riscv: Add the ePMP feature RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-02 Alistair Francis New
[v1,2/8] target/riscv: Define ePMP mseccfg RISC-V: Add support for ePMP v0.9.1 - 2 - --- 2021-04-02 Alistair Francis New
[v1,1/8] target/riscv: Fix the PMP is locked check when using TOR RISC-V: Add support for ePMP v0.9.1 - 1 - --- 2021-04-02 Alistair Francis New
[v1,2/2] sifive_u: Connect the SiFive PWM device Add the SiFive PWM device - - - --- 2021-04-02 Alistair Francis New
[v1,1/2] sifive_u_pwm: Initial commit Add the SiFive PWM device - - - --- 2021-04-02 Alistair Francis New
[v1,1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine [v1,1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine - 1 - --- 2021-04-02 Alistair Francis New
[v2,5/5] target/riscv: Use RISCVException enum for CSR access RISC-V: Convert the CSR access functions to use - 2 - --- 2021-04-01 Alistair Francis New
[v2,4/5] target/riscv: Use the RISCVException enum for CSR operations RISC-V: Convert the CSR access functions to use - 2 - --- 2021-04-01 Alistair Francis New
[v2,3/5] target/riscv: Fix 32-bit HS mode access permissions RISC-V: Convert the CSR access functions to use - 2 - --- 2021-04-01 Alistair Francis New
[v2,2/5] target/riscv: Use the RISCVException enum for CSR predicates RISC-V: Convert the CSR access functions to use - 2 - --- 2021-04-01 Alistair Francis New
[v2,1/5] target/riscv: Convert the RISC-V exceptions to an enum RISC-V: Convert the CSR access functions to use - 2 - --- 2021-04-01 Alistair Francis New
[v1,1/1] hw/opentitan: Update the interrupt layout [v1,1/1] hw/opentitan: Update the interrupt layout - 1 - --- 2021-03-31 Alistair Francis New
[PULL,16/16] target/riscv: Prevent lost illegal instruction exceptions [PULL,01/16] target/riscv: fix vs() to return proper error code - 2 - --- 2021-03-23 Alistair Francis New
[PULL,15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,13/16] hw/block: m25p80: Support fast read for SST flashes [PULL,01/16] target/riscv: fix vs() to return proper error code 1 - - --- 2021-03-23 Alistair Francis New
[PULL,12/16] target/riscv: Add proper two-stage lookup exception detection [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,11/16] target/riscv: Fix read and write accesses to vsip and vsie [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,10/16] hw/riscv: allow ramfb on virt [PULL,01/16] target/riscv: fix vs() to return proper error code - 2 - --- 2021-03-23 Alistair Francis New
[PULL,09/16] hw/riscv: Add fw_cfg support to virt [PULL,01/16] target/riscv: fix vs() to return proper error code - 2 - --- 2021-03-23 Alistair Francis New
[PULL,08/16] target/riscv: Use background registers also for MSTATUS_MPV [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,07/16] target/riscv: Make VSTIP and VSEIP read-only in hip [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,05/16] target/riscv: flush TLB pages if PMP permission has been changed [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,04/16] target/riscv: add log of PMP permission checking [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,03/16] target/riscv: propagate PMP permission to TLB page [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,02/16] hw/char: disable ibex uart receive if the buffer is full [PULL,01/16] target/riscv: fix vs() to return proper error code - 1 - --- 2021-03-23 Alistair Francis New
[PULL,01/16] target/riscv: fix vs() to return proper error code [PULL,01/16] target/riscv: fix vs() to return proper error code - 2 - --- 2021-03-23 Alistair Francis New
[PULL,00/16] riscv-to-apply queue - - - --- 2021-03-23 Alistair Francis New
[v1,5/5] target/riscv: Use RiscVException enum for CSR access RISC-V: Convert the CSR access functions to use - - - --- 2021-03-17 Alistair Francis New
[v1,4/5] target/riscv: Use the RiscVException enum for CSR operations RISC-V: Convert the CSR access functions to use - - - --- 2021-03-17 Alistair Francis New
[v1,3/5] target/riscv: Fix 32-bit HS mode access permissions RISC-V: Convert the CSR access functions to use - - - --- 2021-03-17 Alistair Francis New
[v1,2/5] target/riscv: Use the RiscVException enum for CSR predicates RISC-V: Convert the CSR access functions to use - - - --- 2021-03-17 Alistair Francis New
[v1,1/5] target/riscv: Convert the RISC-V exceptions to an enum RISC-V: Convert the CSR access functions to use - 1 - --- 2021-03-17 Alistair Francis New
[PULL,v2,19/19] hw/riscv: virt: Map high mmio for PCIe [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,18/19] hw/riscv: virt: Limit RAM size in a 32-bit system [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,16/19] hw/riscv: Drop 'struct MemmapEntry' [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,15/19] MAINTAINERS: Add a SiFive machine section [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size 2 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,14/19] goldfish_rtc: re-arm the alarm after migration [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,13/19] docs/system: riscv: Add documentation for sifive_u machine [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,12/19] docs/system: Add RISC-V documentation [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,11/19] docs/system: Sort targets in alphabetical order [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,07/19] hw/ssi: Add SiFive SPI controller support [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,06/19] hw/block: m25p80: Add various ISSI flash information [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - --- 2021-03-04 Alistair Francis New
[PULL,v2,05/19] hw/block: m25p80: Add ISSI SPI flash support [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - --- 2021-03-04 Alistair Francis New
[PULL,v2,04/19] target-riscv: support QMP dump-guest-memory [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 3 - --- 2021-03-04 Alistair Francis New
[PULL,v2,03/19] roms/opensbi: Upgrade from v0.8 to v0.9 [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,00/19] riscv-to-apply queue - - - --- 2021-03-04 Alistair Francis New
[PULL,19/19] hw/riscv: virt: Map high mmio for PCIe [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,18/19] hw/riscv: virt: Limit RAM size in a 32-bit system [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,16/19] hw/riscv: Drop 'struct MemmapEntry' [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,15/19] MAINTAINERS: Add a SiFive machine section [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 2 2 - --- 2021-02-18 Alistair Francis New
[PULL,14/19] goldfish_rtc: re-arm the alarm after migration [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,13/19] docs/system: riscv: Add documentation for sifive_u machine [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,12/19] docs/system: Add RISC-V documentation [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,11/19] docs/system: Sort targets in alphabetical order [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,07/19] hw/ssi: Add SiFive SPI controller support [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,06/19] hw/block: m25p80: Add various ISSI flash information [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - --- 2021-02-18 Alistair Francis New
[PULL,05/19] hw/block: m25p80: Add ISSI SPI flash support [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - --- 2021-02-18 Alistair Francis New
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