Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,04/19] target-riscv: support QMP dump-guest-memory [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 3 - --- 2021-02-18 Alistair Francis New
[PULL,03/19] roms/opensbi: Upgrade from v0.8 to v0.9 [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,01/19] target/riscv: Declare csr_ops[] with a known size [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,00/19] riscv-to-apply queue - - - --- 2021-02-18 Alistair Francis New
[v1,1/1] MAINTAINERS: Add a SiFIve machine section [v1,1/1] MAINTAINERS: Add a SiFIve machine section 2 2 - --- 2021-02-09 Alistair Francis New
[v2,1/1] linux-user/signal: Decode waitid si_code [v2,1/1] linux-user/signal: Decode waitid si_code - 1 1 --- 2021-01-19 Alistair Francis New
[PULL,12/12] riscv: Pass RISCVHartArrayState by pointer [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 2 - --- 2021-01-17 Alistair Francis New
[PULL,11/12] target/riscv: Remove built-in GDB XML files for CSRs [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 - --- 2021-01-17 Alistair Francis New
[PULL,10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 - --- 2021-01-17 Alistair Francis New
[PULL,09/12] target/riscv: Add CSR name in the CSR function table [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 - --- 2021-01-17 Alistair Francis New
[PULL,08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 - --- 2021-01-17 Alistair Francis New
[PULL,07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 - --- 2021-01-17 Alistair Francis New
[PULL,06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 2 - --- 2021-01-17 Alistair Francis New
[PULL,05/12] target/riscv/pmp: Raise exception if no PMP entry is configured [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 - --- 2021-01-17 Alistair Francis New
[PULL,04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 1 --- 2021-01-17 Alistair Francis New
[PULL,03/12] gdb: riscv: Add target description [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 3 - --- 2021-01-17 Alistair Francis New
[PULL,02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 - --- 2021-01-17 Alistair Francis New
[PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 2 - --- 2021-01-17 Alistair Francis New
[PULL,00/12] riscv-to-apply queue - - - --- 2021-01-17 Alistair Francis New
[v1,1/1] riscv: Pass RISCVHartArrayState by pointer [v1,1/1] riscv: Pass RISCVHartArrayState by pointer - 2 - --- 2021-01-15 Alistair Francis New
[v1,1/1] linux-user/signal: Decode waitid si_code [v1,1/1] linux-user/signal: Decode waitid si_code - - 1 --- 2020-12-19 Alistair Francis New
[PULL,23/23] riscv/opentitan: Update the OpenTitan memory layout [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - --- 2020-12-18 Alistair Francis New
[PULL,22/23] hw/riscv: Use the CPU to determine if 32-bit [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - 1 - --- 2020-12-18 Alistair Francis New
[PULL,21/23] target/riscv: cpu: Set XLEN independently from target [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,20/23] target/riscv: csr: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,19/23] target/riscv: cpu_helper: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 3 1 --- 2020-12-18 Alistair Francis New
[PULL,18/23] target/riscv: cpu: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 3 1 --- 2020-12-18 Alistair Francis New
[PULL,17/23] target/riscv: Specify the XLEN for CPUs [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 3 1 --- 2020-12-18 Alistair Francis New
[PULL,16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,15/23] target/riscv: fpu_helper: Match function defs in HELPER macros [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - --- 2020-12-18 Alistair Francis New
[PULL,14/23] hw/riscv: sifive_u: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,13/23] hw/riscv: spike: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 - --- 2020-12-18 Alistair Francis New
[PULL,12/23] hw/riscv: virt: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,11/23] hw/riscv: boot: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,10/23] riscv: virt: Remove target macro conditionals [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,09/23] riscv: spike: Remove target macro conditionals [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 - --- 2020-12-18 Alistair Francis New
[PULL,08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 2 1 --- 2020-12-18 Alistair Francis New
[PULL,07/23] hw/riscv: Expand the is 32-bit check to support more CPUs [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 1 - --- 2020-12-18 Alistair Francis New
[PULL,06/23] intc/ibex_plic: Clear interrupts that occur during claim process [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 --- 2020-12-18 Alistair Francis New
[PULL,05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - 1 - --- 2020-12-18 Alistair Francis New
[PULL,04/23] target/riscv: Fix the bug of HLVX/HLV/HSV [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - 1 - --- 2020-12-18 Alistair Francis New
[PULL,03/23] hw/core/register.c: Don't use '#' flag of printf format [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - 1 - --- 2020-12-18 Alistair Francis New
[PULL,02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 1 - --- 2020-12-18 Alistair Francis New
[PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - 1 - --- 2020-12-18 Alistair Francis New
[PULL,00/23] riscv-to-apply queue - - - --- 2020-12-18 Alistair Francis New
[v4,16/16] hw/riscv: Use the CPU to determine if 32-bit RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-16 Alistair Francis New
[v4,15/16] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,14/16] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,13/16] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 3 1 --- 2020-12-16 Alistair Francis New
[v4,12/16] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 3 1 --- 2020-12-16 Alistair Francis New
[v4,11/16] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess 1 3 1 --- 2020-12-16 Alistair Francis New
[v4,10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,09/16] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess - - - --- 2020-12-16 Alistair Francis New
[v4,08/16] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,07/16] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 2 - --- 2020-12-16 Alistair Francis New
[v4,06/16] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,05/16] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,04/16] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,03/16] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess 1 2 - --- 2020-12-16 Alistair Francis New
[v4,02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess 1 2 1 --- 2020-12-16 Alistair Francis New
[v4,01/16] hw/riscv: Expand the is 32-bit check to support more CPUs RISC-V: Start to remove xlen preprocess 1 1 - --- 2020-12-16 Alistair Francis New
[v1,1/1] riscv/opentitan: Update the OpenTitan memory layout [v1,1/1] riscv/opentitan: Update the OpenTitan memory layout - - - --- 2020-12-15 Alistair Francis New
[v3,15/15] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-14 Alistair Francis New
[v3,14/15] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-14 Alistair Francis New
[v3,13/15] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-14 Alistair Francis New
[v3,12/15] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 2 - --- 2020-12-14 Alistair Francis New
[v3,11/15] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess - 2 1 --- 2020-12-14 Alistair Francis New
[v3,10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-14 Alistair Francis New
[v3,09/15] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess - - - --- 2020-12-14 Alistair Francis New
[v3,08/15] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - --- 2020-12-14 Alistair Francis New
[v3,07/15] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-14 Alistair Francis New
[v3,06/15] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-14 Alistair Francis New
[v3,05/15] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-14 Alistair Francis New
[v3,04/15] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-14 Alistair Francis New
[v3,03/15] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-14 Alistair Francis New
[v3,02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-14 Alistair Francis New
[v3,01/15] hw/riscv: Expand the is 32-bit check to support more CPUs RISC-V: Start to remove xlen preprocess - - - --- 2020-12-14 Alistair Francis New
[v2,15/15] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-08 Alistair Francis New
[v2,14/15] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - --- 2020-12-08 Alistair Francis New
[v2,13/15] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-08 Alistair Francis New
[v2,12/15] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 2 - --- 2020-12-08 Alistair Francis New
[v2,11/15] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess - 2 1 --- 2020-12-08 Alistair Francis New
[v2,10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-08 Alistair Francis New
[v2,09/15] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess - - - --- 2020-12-08 Alistair Francis New
[v2,08/15] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - --- 2020-12-08 Alistair Francis New
[v2,07/15] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-08 Alistair Francis New
[v2,06/15] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-08 Alistair Francis New
[v2,05/15] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-08 Alistair Francis New
[v2,04/15] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-08 Alistair Francis New
[v2,03/15] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - 1 - --- 2020-12-08 Alistair Francis New
[v2,02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess - 1 1 --- 2020-12-08 Alistair Francis New
[v2,01/15] hw/riscv: Expand the is 32-bit check to support more CPUs RISC-V: Start to remove xlen preprocess - - - --- 2020-12-08 Alistair Francis New
[v1,1/1] intc/ibex_plic: Clear interrupts that occur during claim process [v1,1/1] intc/ibex_plic: Clear interrupts that occur during claim process - - 1 --- 2020-12-04 Alistair Francis New
[PULL,2/2] intc/ibex_plic: Ensure we don't loose interrupts [PULL,1/2] intc/ibex_plic: Fix some typos in the comments - - - --- 2020-11-14 Alistair Francis New
[PULL,1/2] intc/ibex_plic: Fix some typos in the comments [PULL,1/2] intc/ibex_plic: Fix some typos in the comments - - - --- 2020-11-14 Alistair Francis New
[PULL,0/2] riscv-to-apply queue - - - --- 2020-11-14 Alistair Francis New
[v1,2/2] intc/ibex_plic: Ensure we don't loose interrupts [v1,1/2] intc/ibex_plic: Fix some typos in the comments - - - --- 2020-11-11 Alistair Francis New
[v1,1/2] intc/ibex_plic: Fix some typos in the comments [v1,1/2] intc/ibex_plic: Fix some typos in the comments - - - --- 2020-11-11 Alistair Francis New
[PULL,6/6] hw/intc/ibex_plic: Clear the claim register when read [PULL,1/6] target/riscv: Add a virtualised MMU Mode - 1 - --- 2020-11-10 Alistair Francis New
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