Show patches with: Submitter = Alistair Francis       |   788 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,24/65] target/riscv: Add Zihintntl extension ISA string to DTS [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,23/65] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 1 1 - --- 2023-09-08 Alistair Francis New
[PULL,22/65] target/riscv: Add Zvksed ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,21/65] crypto: Add SM4 constant parameter CK [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,20/65] crypto: Create sm4_subword [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,19/65] target/riscv: Add Zvkg ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,18/65] target/riscv: Add Zvksh ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,17/65] target/riscv: Add Zvknh ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,16/65] target/riscv: Add Zvkned ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,15/65] target/riscv: Add Zvbb ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,14/65] target/riscv: Refactor some of the generic vector functionality [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,13/65] target/riscv: Refactor translation of vector-widening instruction [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,12/65] target/riscv: Move vector translation checks [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,11/65] target/riscv: Add Zvbc ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - - - --- 2023-09-08 Alistair Francis New
[PULL,10/65] target/riscv: Remove redundant "cpu_vl == 0" checks [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 1 1 - --- 2023-09-08 Alistair Francis New
[PULL,09/65] target/riscv: Refactor vector-vector translation macro [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,08/65] target/riscv: Refactor some of the generic vector functionality [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 1 1 - --- 2023-09-08 Alistair Francis New
[PULL,07/65] target/riscv: Use existing lookup tables for MixColumns [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,06/65] target/riscv: Fix page_check_range use in fault-only-first [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,05/65] target/riscv/cpu.c: add smepmp isa string [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,04/65] target/riscv/cpu.c: add zmmul isa string [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,03/65] hw/char/riscv_htif: Fix the console syscall on big endian hosts [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 4 - --- 2023-09-08 Alistair Francis New
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,00/65] riscv-to-apply queue - - - --- 2023-09-08 Alistair Francis New
[PULL,2/2] hw/riscv/virt.c: change 'aclint' TCG check [PULL,1/2] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() - 2 - --- 2023-08-11 Alistair Francis New
[PULL,1/2] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() [PULL,1/2] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() 1 1 - --- 2023-08-11 Alistair Francis New
[PULL,0/2] riscv-to-apply queue - - - --- 2023-08-11 Alistair Francis New
[RFC,v1,3/3] hw: nvme: ctrl: Process SPDM requests Initial support for SPDM - - - --- 2023-08-08 Alistair Francis New
[RFC,v1,2/3] hw: nvme: ctrl: Initial support for DOE Initial support for SPDM - - - --- 2023-08-08 Alistair Francis New
[RFC,v1,1/3] subprojects: libspdm: Initial support Initial support for SPDM - - - --- 2023-08-08 Alistair Francis New
[PULL,1/1] roms/opensbi: Upgrade from v1.3 to v1.3.1 [PULL,1/1] roms/opensbi: Upgrade from v1.3 to v1.3.1 - 1 1 --- 2023-07-23 Alistair Francis New
[PULL,0/1] riscv-to-apply queue - - - --- 2023-07-23 Alistair Francis New
[PULL,5/5] target/riscv: Fix LMUL check to use VLEN [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 1 - --- 2023-07-19 Alistair Francis New
[PULL,4/5] hw/riscv: Fix typo field in error_report [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 1 - --- 2023-07-19 Alistair Francis New
[PULL,3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 2 1 --- 2023-07-19 Alistair Francis New
[PULL,2/5] riscv/disas: Fix disas output of upper immediates [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section 1 - - --- 2023-07-19 Alistair Francis New
[PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 1 - --- 2023-07-19 Alistair Francis New
[PULL,0/5] riscv-to-apply queue - - - --- 2023-07-19 Alistair Francis New
[PULL,54/54] riscv: Add support for the Zfa extension [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,53/54] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,52/54] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,51/54] target/riscv: update multi-letter extension KVM properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,50/54] target/riscv/cpu.c: create KVM mock properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,49/54] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,48/54] target/riscv/cpu.c: add satp_mode properties earlier [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,47/54] target/riscv/kvm.c: add multi-letter extension KVM properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,46/54] target/riscv/kvm.c: update KVM MISA bits [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,45/54] target/riscv: add KVM specific MISA properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,44/54] target/riscv/cpu: add misa_ext_info_arr[] [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,43/54] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,42/54] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,41/54] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,40/54] target/riscv: use KVM scratch CPUs to init KVM properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,39/54] target/riscv/cpu.c: restrict 'marchid' value [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,38/54] target/riscv/cpu.c: restrict 'mimpid' value [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,37/54] target/riscv/cpu.c: restrict 'mvendorid' value [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,36/54] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,35/54] target/riscv: skip features setup for KVM CPUs [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,34/54] hw/riscv: virt: Convert fdt_load_addr to uint64_t [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,33/54] riscv: Generate devicetree only after machine initialization is complete [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,32/54] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,31/54] target/riscv: Add disas support for BF16 extensions [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 - - --- 2023-07-10 Alistair Francis New
[PULL,30/54] target/riscv: Set the correct exception for implict G-stage translation fail [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,29/54] target/riscv: Expose properties for BF16 extensions [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,28/54] target/riscv: Add support for Zvfbfwma extension [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,27/54] target/riscv: Add support for Zvfbfmin extension [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,26/54] target/riscv: Add support for Zfbfmin extension [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,25/54] target/riscv: Add properties for BF16 extensions [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,24/54] linux-user/riscv: Add syscall riscv_hwprobe [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,23/54] hw/riscv/virt: Restrict ACLINT to TCG [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,22/54] target/riscv: Add RVV registers to log [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,21/54] target/riscv: Only build KVM guest with same wordsize as host [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,20/54] target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,19/54] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 2 1 - --- 2023-07-10 Alistair Francis New
[PULL,18/54] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,17/54] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,16/54] tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,15/54] roms/opensbi: Upgrade from v1.2 to v1.3 [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 1 --- 2023-07-10 Alistair Francis New
[PULL,14/54] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,13/54] target/riscv: Add additional xlen for address when MPRV=1 [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,12/54] target/riscv/cpu.c: fix veyron-v1 CPU properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,11/54] target/riscv: Remove redundant assignment to SXL [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,10/54] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,09/54] target/riscv: Make MPV only work when MPP != PRV_M [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,08/54] disas/riscv: Add support for XThead* instructions [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 - - --- 2023-07-10 Alistair Francis New
[PULL,07/54] disas/riscv: Add support for XVentanaCondOps [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,06/54] disas/riscv: Provide infrastructure for vendor extensions [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,05/54] disas/riscv: Encapsulate opcode_data into decode [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,04/54] disas/riscv: Make rv_op_illegal a shared enum value [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,03/54] disas/riscv: Move types/constants to new header file [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,02/54] target/riscv: Factor out extension tests to cpu_cfg.h [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,00/54] riscv-to-apply queue - - - --- 2023-07-10 Alistair Francis New
[PULL,60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero 1 2 - --- 2023-06-14 Alistair Francis New
[PULL,59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,57/60] target/riscv/vector_helper.c: clean up reference of MTYPE [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,56/60] target/riscv: Fix initialized value for cur_pmmask [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,55/60] util/log: Add vector registers to log [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
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