Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property hw/riscv: opentitan: Fixup resetvec issues - 1 - --- 2022-09-14 Alistair Francis New
[2/3] hw/riscv: opentitan: Fixup resetvec hw/riscv: opentitan: Fixup resetvec issues - - - --- 2022-09-14 Alistair Francis New
[1/3] target/riscv: Set the CPU resetvec directly hw/riscv: opentitan: Fixup resetvec issues - 2 - --- 2022-09-14 Alistair Francis New
[PULL,44/44] target/riscv: Update the privilege field for sscofpmf CSRs [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,43/44] hw/riscv: virt: Add PMU DT node to the device tree [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 - - --- 2022-09-07 Alistair Francis New
[PULL,42/44] target/riscv: Add few cache related PMU events [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 1 --- 2022-09-07 Alistair Francis New
[PULL,41/44] target/riscv: Simplify counter predicate function [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 1 - --- 2022-09-07 Alistair Francis New
[PULL,40/44] target/riscv: Add sscofpmf extension support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 1 --- 2022-09-07 Alistair Francis New
[PULL,39/44] target/riscv: Add vstimecmp support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,38/44] target/riscv: Add stimecmp support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,37/44] hw/intc: Move mtimer/mtimecmp to aclint [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 3 - --- 2022-09-07 Alistair Francis New
[PULL,36/44] target/riscv: Use official extension names for AIA CSRs [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,35/44] target/riscv: Add xicondops in ISA entry [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,34/44] hw/core: fix platform bus node name [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,33/44] hw/riscv: virt: fix syscon subnode paths [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,32/44] hw/riscv: virt: fix the plic's address cells [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,31/44] hw/riscv: virt: fix uart node name [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,30/44] target/riscv: Remove additional priv version check for mcountinhibit [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 1 --- 2022-09-07 Alistair Francis New
[PULL,29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,28/44] hw/riscv: opentitan: bump opentitan version [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,25/44] target/riscv: Add Zihintpause support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 1 --- 2022-09-07 Alistair Francis New
[PULL,24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 3 - --- 2022-09-07 Alistair Francis New
[PULL,23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,17/44] target/riscv: rvv: Add mask agnostic for vx instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,16/44] target/riscv: rvv: Add mask agnostic for vector load / store instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,15/44] target/riscv: rvv: Add mask agnostic for vv instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 3 - --- 2022-09-07 Alistair Francis New
[PULL,14/44] docs: List kvm as a supported accelerator on RISC-V [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,12/44] roms/opensbi: Upgrade from v1.0 to v1.1 [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,11/44] target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,10/44] target/riscv: Fix checks in hmode/hmode32 [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,09/44] target/riscv: Add check for csrs existed with U extension [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,07/44] target/riscv: H extension depends on I extension [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,06/44] target/riscv: Add check for supported privilege mode combinations [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,05/44] hw/riscv: virt: pass random seed to fdt [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,04/44] target/riscv: move zmmul out of the experimental properties [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,03/44] target/riscv: fix shifts shamt value for rv128c [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,02/44] target/riscv: Force disable extensions if priv spec version does not match [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 1 - --- 2022-09-07 Alistair Francis New
[PULL,00/44] riscv-to-apply queue - - - --- 2022-09-07 Alistair Francis New
MAINTAINERS: Add myself as hw/core/uboot_image.h maintainer MAINTAINERS: Add myself as hw/core/uboot_image.h maintainer - 1 - --- 2022-05-09 Alistair Francis New
[PULL,v2,12/12] hw/riscv/boot: Check the error of fdt_pack() [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,11/12] hw/riscv: opentitan: Add the flash alias [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,09/12] char: ibex_uart: Update the register layout [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,05/12] target/riscv: hardwire bits in hideleg and hedeleg [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 2 - --- 2021-07-15 Alistair Francis New
[PULL,v2,04/12] docs/system: riscv: Add documentation for virt machine [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-15 Alistair Francis New
[PULL,v2,01/12] target/riscv: pmp: Fix some typos [PULL,v2,01/12] target/riscv: pmp: Fix some typos - 2 - --- 2021-07-15 Alistair Francis New
[PULL,v2,00/12] riscv-to-apply queue - - - --- 2021-07-15 Alistair Francis New
[v2,1/1] hw/riscv/boot: Check the error of fdt_pack() [v2,1/1] hw/riscv/boot: Check the error of fdt_pack() - 1 - --- 2021-07-14 Alistair Francis New
[v2,5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-14 Alistair Francis New
[v2,4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 3 1 --- 2021-07-14 Alistair Francis New
[v2,3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-14 Alistair Francis New
[v2,2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 1 --- 2021-07-14 Alistair Francis New
[v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines [v2,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 3 1 --- 2021-07-14 Alistair Francis New
[v1,1/1] hw/riscv/boot: Check the error of fdt_pack() [v1,1/1] hw/riscv/boot: Check the error of fdt_pack() - 1 - --- 2021-07-14 Alistair Francis New
[PULL,11/11] hw/riscv: opentitan: Add the flash alias [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,09/11] char: ibex_uart: Update the register layout [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,05/11] target/riscv: hardwire bits in hideleg and hedeleg [PULL,01/11] target/riscv: pmp: Fix some typos - 2 - --- 2021-07-12 Alistair Francis New
[PULL,04/11] docs/system: riscv: Add documentation for virt machine [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines [PULL,01/11] target/riscv: pmp: Fix some typos - 1 - --- 2021-07-12 Alistair Francis New
[PULL,01/11] target/riscv: pmp: Fix some typos [PULL,01/11] target/riscv: pmp: Fix some typos - 2 - --- 2021-07-12 Alistair Francis New
[PULL,00/11] riscv-to-apply queue - - - --- 2021-07-12 Alistair Francis New
[v2,3/3] hw/riscv: opentitan: Add the flash alias Updates to the OpenTitan machine - 1 - --- 2021-07-09 Alistair Francis New
[v2,2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Updates to the OpenTitan machine - 1 - --- 2021-07-09 Alistair Francis New
[v2,1/3] char: ibex_uart: Update the register layout Updates to the OpenTitan machine - 1 - --- 2021-07-09 Alistair Francis New
[v1,5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-09 Alistair Francis New
[v1,4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-09 Alistair Francis New
[v1,3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-09 Alistair Francis New
[v1,2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - - --- 2021-07-09 Alistair Francis New
[v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 3 - --- 2021-07-09 Alistair Francis New
[v1,3/3] hw/riscv: opentitan: Add the flash alias Updates to the OpenTitan machine - - - --- 2021-07-02 Alistair Francis New
[v1,2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Updates to the OpenTitan machine - 1 - --- 2021-07-02 Alistair Francis New
[v1,1/3] char: ibex_uart: Update the register layout Updates to the OpenTitan machine - 1 - --- 2021-07-02 Alistair Francis New
[PULL,7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 1 - --- 2021-06-24 Alistair Francis New
[PULL,6/7] hw/timer: Initial commit of Ibex Timer [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 1 - --- 2021-06-24 Alistair Francis New
[PULL,5/7] hw/char/ibex_uart: Make the register layout private [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 1 - --- 2021-06-24 Alistair Francis New
[PULL,4/7] hw/char: QOMify sifive_uart [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 2 - --- 2021-06-24 Alistair Francis New
[PULL,3/7] hw/char: Consistent function names for sifive_uart [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 2 - --- 2021-06-24 Alistair Francis New
[PULL,2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 1 1 --- 2021-06-24 Alistair Francis New
[PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa [PULL,1/7] target/riscv: Use target_ulong for the DisasContext misa - 1 - --- 2021-06-24 Alistair Francis New
[PULL,0/7] riscv-to-apply queue - - - --- 2021-06-24 Alistair Francis New
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