Show patches with: Series = Add RISC-V Hypervisor Extension       |    State = Action Required       |   23 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[RFC,v1,23/23] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,22/23] target/riscv: Call the second stage MMU in virtualisation mode Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,21/23] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,20/23] target/riscv: Allow specifying number of MMU stages Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,19/23] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,18/23] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,17/23] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,16/23] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,15/23] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,14/23] riscv: plic: Remove unused interrupt functions Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,13/23] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,12/23] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,11/23] target/riscv: Add background register swapping function Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,10/23] target/riscv: Add background CSRs accesses Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,09/23] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,08/23] target/riscv: Add support for background interrupt setting Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,07/23] target/riscv: Remove strict perm checking for CSR R/W Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,06/23] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,05/23] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,04/23] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,03/23] target/riscv: Add the virtulisation mode Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,02/23] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,01/23] target/riscv: Don't set write permissions on dirty PTEs Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New