Show patches with: Series = Add RISC-V Hypervisor Extension       |    State = Action Required       |   27 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,27/27] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,26/27] target/riscv: Call the second stage MMU in virtualisation mode Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,25/27] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,24/27] target/riscv: Allow specifying number of MMU stages Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,23/27] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,22/27] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,21/27] target/riscv: Mark both sstatus and bsstatus as dirty Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,20/27] target/riscv: Disable guest FP support based on backgrond status Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,19/27] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,18/27] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,17/27] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,16/27] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,15/27] riscv: plic: Remove unused interrupt functions Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,14/27] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,13/27] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,12/27] target/riscv: Add background register swapping function Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,11/27] target/riscv: Add background CSRs accesses Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,10/27] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,09/27] target/riscv: Add support for background interrupt setting Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,08/27] target/riscv: Create function to test if FP is enabled Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,07/27] target/riscv: Remove strict perm checking for CSR R/W Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,06/27] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,05/27] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,04/27] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,03/27] target/riscv: Add the virtulisation mode Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,02/27] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,01/27] target/riscv: Don't set write permissions on dirty PTEs Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New