Show patches with: Series = [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props       |   34 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,34/34] hw/riscv: Load OpenSBI as the default firmware [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,33/34] roms: Add OpenSBI version 0.3 [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,32/34] hw/riscv: Extend the kernel loading support [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,31/34] hw/riscv: Add support for loading a firmware [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,30/34] hw/riscv: Split out the boot functions [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,29/34] riscv: sifive_u: Update the plic hart config to support multicore [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,28/34] riscv: sifive_u: Do not create hard-coded phandles in DT [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,27/34] disas/riscv: Fix `rdinstreth` constraint [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,26/34] disas/riscv: Disassemble reserved compressed encodings as illegal [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,25/34] riscv: virt: Add cpu-topology DT node. [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,24/34] RISC-V: Update syscall list for 32-bit support. [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,23/34] RISC-V: Clear load reservations on context switch and SC [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 2 - --- 2019-06-28 Palmer Dabbelt New
[PULL,22/34] RISC-V: Add support for the Zicsr extension [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,21/34] RISC-V: Add support for the Zifencei extension [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,20/34] target/riscv: Add support for disabling/enabling Counters [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,19/34] target/riscv: Remove user version information [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,18/34] target/riscv: Require either I or E base extension [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - - --- 2019-06-28 Palmer Dabbelt New
[PULL,16/34] target/riscv: Set privledge spec 1.11.0 as default [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,15/34] target/riscv: Add the mcountinhibit CSR [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,14/34] target/riscv: Add the privledge spec version 1.11.0 [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,13/34] target/riscv: Restructure deprecatd CPUs [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,12/34] RISC-V: Fix a memory leak when realizing a sifive_e [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 2 - --- 2019-06-28 Palmer Dabbelt New
[PULL,11/34] riscv: virt: Correct pci "bus-range" encoding [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,10/34] RISC-V: Fix a PMP check with the correct access size [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,08/34] RISC-V: Check PMP during Page Table Walks [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,07/34] RISC-V: Check for the effective memory privilege mode during PMP checks [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,06/34] RISC-V: Raise access fault exceptions on PMP violations [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,05/34] RISC-V: Only Check PMP if MMU translation succeeds [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,04/34] target/riscv: Implement riscv_cpu_unassigned_access [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,03/34] target/riscv: Fix PMP range boundary address bug [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 2 - --- 2019-06-28 Palmer Dabbelt New
[PULL,02/34] sifive_prci: Read and write PRCI registers [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - - --- 2019-06-28 Palmer Dabbelt New