Show patches with: Series = [PULL,01/19] target/riscv: Declare csr_ops[] with a known size       |    State = Action Required       |   19 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,19/19] hw/riscv: virt: Map high mmio for PCIe [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,18/19] hw/riscv: virt: Limit RAM size in a 32-bit system [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,16/19] hw/riscv: Drop 'struct MemmapEntry' [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,15/19] MAINTAINERS: Add a SiFive machine section [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 2 2 - --- 2021-02-18 Alistair Francis New
[PULL,14/19] goldfish_rtc: re-arm the alarm after migration [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,13/19] docs/system: riscv: Add documentation for sifive_u machine [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,12/19] docs/system: Add RISC-V documentation [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,11/19] docs/system: Sort targets in alphabetical order [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,07/19] hw/ssi: Add SiFive SPI controller support [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,06/19] hw/block: m25p80: Add various ISSI flash information [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - --- 2021-02-18 Alistair Francis New
[PULL,05/19] hw/block: m25p80: Add ISSI SPI flash support [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - --- 2021-02-18 Alistair Francis New
[PULL,04/19] target-riscv: support QMP dump-guest-memory [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 3 - --- 2021-02-18 Alistair Francis New
[PULL,03/19] roms/opensbi: Upgrade from v0.8 to v0.9 [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 1 - --- 2021-02-18 Alistair Francis New
[PULL,02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New
[PULL,01/19] target/riscv: Declare csr_ops[] with a known size [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - 2 - --- 2021-02-18 Alistair Francis New