Show patches with: Series = [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines       |    State = Action Required       |   5 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-09 Alistair Francis New
[v1,4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-09 Alistair Francis New
[v1,3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-07-09 Alistair Francis New
[v1,2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - - --- 2021-07-09 Alistair Francis New
[v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines [v1,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 3 - --- 2021-07-09 Alistair Francis New