Show patches with: Series = Misc RISC-V fixes       |    State = Action Required       |   5 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,5/5] sifive_uart: Implement interrupt pending register Misc RISC-V fixes - 2 - --- 2018-12-14 Alistair Francis New
[v1,4/5] RISC-V: Enable second UART on sifive_e and sifive_u Misc RISC-V fixes - 1 - --- 2018-12-14 Alistair Francis New
[v1,3/5] RISC-V: Fix PLIC pending bitfield reads Misc RISC-V fixes - 1 - --- 2018-12-14 Alistair Francis New
[v1,2/5] RISC-V: Fix CLINT timecmp low 32-bit writes Misc RISC-V fixes - 1 - --- 2018-12-14 Alistair Francis New
[v1,1/5] RISC-V: Add hartid and \n to interrupt logging Misc RISC-V fixes - 1 - --- 2018-12-14 Alistair Francis New