Show patches with: Series = Support UXL filed in xstatus       |   20 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v4,20/20] target/riscv: Enable uxl field write Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,19/20] target/riscv: Adjust scalar reg in vector with XLEN Support UXL filed in xstatus - - - --- 2021-11-11 LIU Zhiwei New
[v4,18/20] target/riscv: Adjust vector address with mask Support UXL filed in xstatus 1 - - --- 2021-11-11 LIU Zhiwei New
[v4,17/20] target/riscv: Fix check range for first fault only Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,16/20] target/riscv: Ajdust vector atomic check with XLEN Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,15/20] target/riscv: Remove VILL field in VTYPE Support UXL filed in xstatus 1 1 - --- 2021-11-11 LIU Zhiwei New
[v4,14/20] target/riscv: Adjust vsetvl according to XLEN Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,13/20] target/riscv: Fix RESERVED field length in VTYPE Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,12/20] target/riscv: Split out the vill from vtype Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,11/20] target/riscv: Split pm_enabled into mask and base Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,10/20] target/riscv: Calculate address according to XLEN Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,08/20] target/riscv: Create current pm fields in env Support UXL filed in xstatus - 1 - --- 2021-11-11 LIU Zhiwei New
[v4,07/20] target/riscv: Adjust csr write mask with XLEN Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,06/20] target/riscv: Relax debug check for pm write Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,05/20] target/riscv: Use gdb xml according to max mxlen Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,04/20] target/riscv: Extend pc for runtime pc write Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,03/20] target/riscv: Ignore the pc bits above XLEN Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,02/20] target/riscv: Sign extend pc for different XLEN Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,01/20] target/riscv: Don't save pc when exception return Support UXL filed in xstatus - 2 - --- 2021-11-11 LIU Zhiwei New