Show patches with: Series = Improve RISC-V Debug support       |   9 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[9/9] target/riscv: debug: Add initial support of type 6 trigger Improve RISC-V Debug support - 1 - --- 2022-06-10 Frank Chang New
[8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers Improve RISC-V Debug support - - - --- 2022-06-10 Frank Chang New
[7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger Improve RISC-V Debug support - 1 - --- 2022-06-10 Frank Chang New
[6/9] target/riscv: debug: Create common trigger actions function Improve RISC-V Debug support - - - --- 2022-06-10 Frank Chang New
[5/9] target/riscv: debug: Introduce tinfo CSR Improve RISC-V Debug support - 1 - --- 2022-06-10 Frank Chang New
[4/9] target/riscv: debug: Restrict the range of tselect value can be written Improve RISC-V Debug support - 1 - --- 2022-06-10 Frank Chang New
[3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Improve RISC-V Debug support - - - --- 2022-06-10 Frank Chang New
[2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content Improve RISC-V Debug support - 1 - --- 2022-06-10 Frank Chang New
[1/9] target/riscv: debug: Determine the trigger type from tdata1.type Improve RISC-V Debug support - 1 - --- 2022-06-10 Frank Chang New