Show patches with: Series = [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()       |    State = Action Required       |   44 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,44/44] target/riscv: Update the privilege field for sscofpmf CSRs [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,43/44] hw/riscv: virt: Add PMU DT node to the device tree [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 - - --- 2022-09-07 Alistair Francis New
[PULL,42/44] target/riscv: Add few cache related PMU events [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 1 --- 2022-09-07 Alistair Francis New
[PULL,41/44] target/riscv: Simplify counter predicate function [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 1 - --- 2022-09-07 Alistair Francis New
[PULL,40/44] target/riscv: Add sscofpmf extension support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 1 --- 2022-09-07 Alistair Francis New
[PULL,39/44] target/riscv: Add vstimecmp support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,38/44] target/riscv: Add stimecmp support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,37/44] hw/intc: Move mtimer/mtimecmp to aclint [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 3 - --- 2022-09-07 Alistair Francis New
[PULL,36/44] target/riscv: Use official extension names for AIA CSRs [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,35/44] target/riscv: Add xicondops in ISA entry [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,34/44] hw/core: fix platform bus node name [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,33/44] hw/riscv: virt: fix syscon subnode paths [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,32/44] hw/riscv: virt: fix the plic's address cells [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,31/44] hw/riscv: virt: fix uart node name [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,30/44] target/riscv: Remove additional priv version check for mcountinhibit [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 1 --- 2022-09-07 Alistair Francis New
[PULL,29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,28/44] hw/riscv: opentitan: bump opentitan version [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,25/44] target/riscv: Add Zihintpause support [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 1 --- 2022-09-07 Alistair Francis New
[PULL,24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 3 - --- 2022-09-07 Alistair Francis New
[PULL,23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,17/44] target/riscv: rvv: Add mask agnostic for vx instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,16/44] target/riscv: rvv: Add mask agnostic for vector load / store instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 2 - --- 2022-09-07 Alistair Francis New
[PULL,15/44] target/riscv: rvv: Add mask agnostic for vv instructions [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 3 - --- 2022-09-07 Alistair Francis New
[PULL,14/44] docs: List kvm as a supported accelerator on RISC-V [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,12/44] roms/opensbi: Upgrade from v1.0 to v1.1 [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,11/44] target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,10/44] target/riscv: Fix checks in hmode/hmode32 [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,09/44] target/riscv: Add check for csrs existed with U extension [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,07/44] target/riscv: H extension depends on I extension [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,06/44] target/riscv: Add check for supported privilege mode combinations [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,05/44] hw/riscv: virt: pass random seed to fdt [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,04/44] target/riscv: move zmmul out of the experimental properties [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,03/44] target/riscv: fix shifts shamt value for rv128c [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 2 - --- 2022-09-07 Alistair Francis New
[PULL,02/44] target/riscv: Force disable extensions if priv spec version does not match [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() - 1 - --- 2022-09-07 Alistair Francis New
[PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 1 1 - --- 2022-09-07 Alistair Francis New