Show patches with: Series = target/riscv: Convert to decodetree       |    State = Action Required       |   35 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v7,35/35] target/riscv: Remaining rvc insn reuse 32 bit translators target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,31/35] target/riscv: Convert @cs_2 insns to share translation functions target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,30/35] target/riscv: Remove decode_RV32_64G() target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,29/35] target/riscv: Remove gen_system() target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,28/35] target/riscv: Rename trans_arith to gen_arith target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,27/35] target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,26/35] target/riscv: Remove shift and slt insn manual decoding target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,23/35] target/riscv: Remove manual decoding from gen_store() target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,22/35] target/riscv: Remove manual decoding from gen_load() target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,21/35] target/riscv: Remove manual decoding from gen_branch() target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,20/35] target/riscv: Remove gen_jalr() target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert to decodetree - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,16/35] target/riscv: Convert RV priv insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,15/35] target/riscv: Convert RV64D insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,14/35] target/riscv: Convert RV32D insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,13/35] target/riscv: Convert RV64F insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,12/35] target/riscv: Convert RV32F insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,11/35] target/riscv: Convert RV64A insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,10/35] target/riscv: Convert RV32A insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,09/35] target/riscv: Convert RVXM insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,08/35] target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,07/35] target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,06/35] target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,05/35] target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,04/35] target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,03/35] target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert to decodetree 1 2 - --- 2019-02-13 Palmer Dabbelt New
[v7,02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert to decodetree 1 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,01/35] target/riscv: Move CPURISCVState pointer to DisasContext target/riscv: Convert to decodetree - 3 - --- 2019-02-13 Palmer Dabbelt New