Show patches with: Series = Add RISC-V ISA extension smcntrpmf support       |    State = Action Required       |   11 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v7,11/11] target/riscv: Do not setup pmu timer if OF is disabled Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Kumar Patra New
[v7,10/11] target/riscv: More accurately model priv mode filtering. Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Kumar Patra New
[v7,09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Kumar Patra New
[v7,08/11] target/riscv: Enforce WARL behavior for scounteren/hcounteren Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Kumar Patra New
[v7,07/11] target/riscv: Save counter values during countinhibit update Add RISC-V ISA extension smcntrpmf support 1 1 - --- 2024-06-26 Atish Kumar Patra New
[v7,06/11] target/riscv: Implement privilege mode filtering for cycle/instret Add RISC-V ISA extension smcntrpmf support 1 1 - --- 2024-06-26 Atish Kumar Patra New
[v7,05/11] target/riscv: Add cycle & instret privilege mode filtering support Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Kumar Patra New
[v7,04/11] target/riscv: Add cycle & instret privilege mode filtering definitions Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Kumar Patra New
[v7,03/11] target/riscv: Add cycle & instret privilege mode filtering properties Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Kumar Patra New
[v7,02/11] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Kumar Patra New
[v7,01/11] target/riscv: Combine set_mode and set_virt functions. Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Kumar Patra New