Show patches with: Submitter = Artyom Tarasenko       |   132 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,3/3] hw/isa/i82378.c: use 1900 as a base year Improve 40p, make AIX 5.1 boot - 1 - --- 2019-05-04 Artyom Tarasenko New
[2/3] 40p and prep: implement PCI bus mastering Improve 40p, make AIX 5.1 boot - 1 - --- 2019-05-04 Artyom Tarasenko New
[v2,1/3] lsi53c895a: hide 53c895a registers in 53c810 Improve 40p, make AIX 5.1 boot - - - --- 2019-05-04 Artyom Tarasenko New
[4/4] hw/isa/i82378.c: use 1900 as a base year Improve 40p, make AIX 5.1 boot - 1 - --- 2019-04-12 Artyom Tarasenko New
[3/4] target/ppc: improve performance of large BAT invalidations Improve 40p, make AIX 5.1 boot - 1 - --- 2019-04-12 Artyom Tarasenko New
[2/4] 40p and prep: implement PCI bus mastering Improve 40p, make AIX 5.1 boot - 1 - --- 2019-04-12 Artyom Tarasenko New
[1/4] lsi53c895a: hide 53c895a registers in 53c810 Improve 40p, make AIX 5.1 boot - - - --- 2019-04-12 Artyom Tarasenko New
[PULL,2/2] niagara: check if a serial port is available - 1 - --- 2017-02-26 Artyom Tarasenko New
[PULL,1/2] niagara: fail if a firmware file is missing - - - --- 2017-02-26 Artyom Tarasenko New
[v2,2/2] niagara: check if a serial port is available - 1 - --- 2017-01-24 Artyom Tarasenko New
[v2,1/2] niagara: fail if a firmware file is missing - - - --- 2017-01-24 Artyom Tarasenko New
[2/2] niagara: check if a serial port is available - 1 - --- 2017-01-23 Artyom Tarasenko New
[1/2] niagara: fail if a firmware file is missing - - - --- 2017-01-23 Artyom Tarasenko New
[PULL,30/30] target-sparc: fix up niagara machine - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,29/30] target-sparc: move common cpu initialisation routines to sparc64.c - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,28/30] target-sparc: implement sun4v RTC - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,25/30] target-sparc: implement UA2005 ASI_MMU (0x21) - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,24/30] target-sparc: add more registers to dump_mmu - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,23/30] target-sparc: implement auto-demapping for UA2005 CPUs - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,22/30] target-sparc: allow 256M sized pages - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,21/30] target-sparc: simplify ultrasparc_tsb_pointer - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,20/30] target-sparc: implement UA2005 TSB Pointers - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,18/30] target-sparc: replace the last tlb entry when no free entries left - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,15/30] target-sparc: use direct address translation in hyperprivileged mode - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,14/30] target-sparc: fix immediate UA2005 traps - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,12/30] target-sparc: implement UA2005 GL register - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,11/30] target-sparc: implement UA2005 hypervisor traps - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,10/30] target-sparc: hypervisor mode takes over nucleus mode - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,08/30] target-sparc: implement UA2005 scratchpad registers - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,05/30] target-sparc: add UltraSPARC T1 TLB #defines - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,04/30] target-sparc: add UA2005 TTE bit #defines - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,03/30] target-sparc: use explicit mmu register pointers - 1 - --- 2017-01-18 Artyom Tarasenko New
[PULL,02/30] target-sparc: store cpu super- and hypervisor flags in TB - - - --- 2017-01-18 Artyom Tarasenko New
[PULL,01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode - - - --- 2017-01-18 Artyom Tarasenko New
[v2,30/30] target-sparc: fix up niagara machine - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,29/30] target-sparc: move common cpu initialisation routines to sparc64.c - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,28/30] target-sparc: implement sun4v RTC - - - --- 2017-01-11 Artyom Tarasenko New
[v2,27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs - - - --- 2017-01-11 Artyom Tarasenko New
[v2,25/30] target-sparc: implement UA2005 ASI_MMU (0x21) - - - --- 2017-01-11 Artyom Tarasenko New
[v2,24/30] target-sparc: add more registers to dump_mmu - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,23/30] target-sparc: implement auto-demapping for UA2005 CPUs - - - --- 2017-01-11 Artyom Tarasenko New
[v2,22/30] target-sparc: allow 256M sized pages - - - --- 2017-01-11 Artyom Tarasenko New
[v2,21/30] target-sparc: simplify ultrasparc_tsb_pointer - - - --- 2017-01-11 Artyom Tarasenko New
[v2,20/30] target-sparc: implement UA2005 TSB Pointers - - - --- 2017-01-11 Artyom Tarasenko New
[v2,19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs - - - --- 2017-01-11 Artyom Tarasenko New
[v2,18/30] target-sparc: replace the last tlb entry when no free entries left - - - --- 2017-01-11 Artyom Tarasenko New
[v2,17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode - - - --- 2017-01-11 Artyom Tarasenko New
[v2,15/30] target-sparc: use direct address translation in hyperprivileged mode - - - --- 2017-01-11 Artyom Tarasenko New
[v2,14/30] target-sparc: fix immediate UA2005 traps - - - --- 2017-01-11 Artyom Tarasenko New
[v2,13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,12/30] target-sparc: implement UA2005 GL register - - - --- 2017-01-11 Artyom Tarasenko New
[v2,11/30] target-sparc: implement UA2005 hypervisor traps - - - --- 2017-01-11 Artyom Tarasenko New
[v2,10/30] target-sparc: hypervisor mode takes over nucleus mode - - - --- 2017-01-11 Artyom Tarasenko New
[v2,09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,08/30] target-sparc: implement UA2005 scratchpad registers - - - --- 2017-01-11 Artyom Tarasenko New
[v2,07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,05/30] target-sparc: add UltraSPARC T1 TLB #defines - - - --- 2017-01-11 Artyom Tarasenko New
[v2,04/30] target-sparc: add UA2005 TTE bit #defines - - - --- 2017-01-11 Artyom Tarasenko New
[v2,03/30] target-sparc: use explicit mmu register pointers - 1 - --- 2017-01-11 Artyom Tarasenko New
[v2,02/30] target-sparc: store cpu super- and hypervisor flags in TB - - - --- 2017-01-11 Artyom Tarasenko New
[v2,01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode - - - --- 2017-01-11 Artyom Tarasenko New
[v1,30/30] target-sparc: fix up niagara machine - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,29/30] target-sparc: move common cpu initialisation routines to sparc64.c - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,28/30] target-sparc: implement sun4v RTC - - - --- 2016-11-04 Artyom Tarasenko New
[v1,27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs - - - --- 2016-11-04 Artyom Tarasenko New
[v1,25/30] target-sparc: implement UA2005 ASI_MMU (0x21) - - - --- 2016-11-04 Artyom Tarasenko New
[v1,24/30] target-sparc: add more registers to dump_mmu - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,23/30] target-sparc: implement auto-demapping for UA2005 CPUs - - - --- 2016-11-04 Artyom Tarasenko New
[v1,22/30] target-sparc: allow 256M sized pages - - - --- 2016-11-04 Artyom Tarasenko New
[v1,21/30] target-sparc: simplify ultrasparc_tsb_pointer - - - --- 2016-11-04 Artyom Tarasenko New
[v1,20/30] target-sparc: implement UA2005 TSB Pointers - - - --- 2016-11-04 Artyom Tarasenko New
[v1,19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs - - - --- 2016-11-04 Artyom Tarasenko New
[v1,18/30] target-sparc: replace the last tlb entry when no free entries left - - - --- 2016-11-04 Artyom Tarasenko New
[v1,17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode - - - --- 2016-11-04 Artyom Tarasenko New
[v1,15/30] target-sparc: use direct address translation in hyperprivileged mode - - - --- 2016-11-04 Artyom Tarasenko New
[v1,14/30] target-sparc: fix immediate UA2005 traps - - - --- 2016-11-04 Artyom Tarasenko New
[v1,13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,12/30] target-sparc: implement UA2005 GL register - - - --- 2016-11-04 Artyom Tarasenko New
[v1,11/30] target-sparc: implement UA2005 hypervisor traps - - - --- 2016-11-04 Artyom Tarasenko New
[v1,10/30] target-sparc: hypervisor mode takes over nucleus mode - - - --- 2016-11-04 Artyom Tarasenko New
[v1,09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,08/30] target-sparc: implement UA2005 scratchpad registers - - - --- 2016-11-04 Artyom Tarasenko New
[v1,07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,05/30] target-sparc: add UltraSPARC T1 TLB #defines - - - --- 2016-11-04 Artyom Tarasenko New
[v1,04/30] target-sparc: add UA2005 TTE bit #defines - - - --- 2016-11-04 Artyom Tarasenko New
[v1,03/30] target-sparc: use explicit mmu register pointers - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,02/30] target-sparc: store cpu super- and hypervisor flags in TB - 1 - --- 2016-11-04 Artyom Tarasenko New
[v1,01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode - - - --- 2016-11-04 Artyom Tarasenko New
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