Show patches with: Submitter = Michael Clark       |   450 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2] elf: Add RISC-V PSABI ELF header defines - 1 - --- 2018-05-25 Michael Clark New
RISC-V: Correct typo in RV32 perf counters - 1 - --- 2018-05-25 Michael Clark New
[v1,30/30] RISC-V: Support separate firmware and kernel payload - - - --- 2018-05-23 Michael Clark New
[v1,29/30] RISC-V: Don't add NULL bootargs to device-tree - 1 - --- 2018-05-23 Michael Clark New
[v1,28/30] RISC-V: linux-user support for RVE ABI - - - --- 2018-05-23 Michael Clark New
[v1,27/30] elf: Add RISC-V PSABI ELF header defines - - - --- 2018-05-23 Michael Clark New
[v1,26/30] RISC-V: Remove unnecessary disassembler constraints 1 - - --- 2018-05-23 Michael Clark New
[v1,25/30] RISC-V: Enable second UART on sifive_e and sifive_u - - - --- 2018-05-23 Michael Clark New
[v1,24/30] RISC-V: Fix PLIC pending bitfield reads - 1 - --- 2018-05-23 Michael Clark New
[v1,23/30] RISC-V: Fix CLINT timecmp low 32-bit writes - 1 - --- 2018-05-23 Michael Clark New
[v1,22/30] RISC-V: Add misa runtime write support - - - --- 2018-05-23 Michael Clark New
[v1,21/30] RISC-V: Add misa.MAFD checks to translate - - - --- 2018-05-23 Michael Clark New
[v1,20/30] RISC-V: Add misa to DisasContext - 2 - --- 2018-05-23 Michael Clark New
[v1,19/30] RISC-V: Allow interrupt controllers to claim interrupts - - - --- 2018-05-23 Michael Clark New
[v1,18/30] RISC-V: Add missing free for plic_hart_config - 2 - --- 2018-05-23 Michael Clark New
[v1,17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC - 2 - --- 2018-05-23 Michael Clark New
[v1,16/30] RISC-V: Use riscv prefix consistently on cpu helpers - 2 - --- 2018-05-23 Michael Clark New
[v1,15/30] RISC-V: Add hartid and \n to interrupt logging - 2 - --- 2018-05-23 Michael Clark New
[v1,14/30] RISC-V: Add public API for the CSR dispatch table - - - --- 2018-05-23 Michael Clark New
[v1,13/30] RISC-V: Implement mstatus.TSR/TW/TVM - - - --- 2018-05-23 Michael Clark New
[v1,12/30] RISC-V: Mark mstatus.fs dirty - 2 - --- 2018-05-23 Michael Clark New
[v1,11/30] RISC-V: Split out mstatus_fs from tb_flags - 3 - --- 2018-05-23 Michael Clark New
[v1,10/30] RISC-V: Implement existential predicates for CSRs - - - --- 2018-05-23 Michael Clark New
[v1,09/30] RISC-V: Implement atomic mip/sip CSR updates 1 - - --- 2018-05-23 Michael Clark New
[v1,08/30] RISC-V: Implement modular CSR helper interface - - - --- 2018-05-23 Michael Clark New
[v1,07/30] RISC-V: Update CSR and interrupt definitions - 1 - --- 2018-05-23 Michael Clark New
[v1,06/30] RISC-V: Move non-ops from op_helper to cpu_helper - 3 - --- 2018-05-23 Michael Clark New
[v1,05/30] RISC-V: Allow setting and clearing multiple irqs - 2 - --- 2018-05-23 Michael Clark New
[v1,04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending - 2 - --- 2018-05-23 Michael Clark New
[v1,03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps - 2 - --- 2018-05-23 Michael Clark New
[v1,02/30] RISC-V: Improve page table walker spec compliance - 1 - --- 2018-05-23 Michael Clark New
[v1,01/30] RISC-V: Update address bits to support sv39 and sv48 - 1 - --- 2018-05-23 Michael Clark New
[PULL,3/3] riscv: requires libfdt - 3 - --- 2018-05-09 Michael Clark New
[PULL,2/3] riscv: htif: increase the priority of the htif subregion - 1 - --- 2018-05-09 Michael Clark New
[PULL,1/3] riscv: spike: allow base == 0 - 1 - --- 2018-05-09 Michael Clark New
[v1,6/6] target/riscv: add misa to DisasContext - - - --- 2018-05-09 Michael Clark New
[v1,5/6] target/riscv: convert to TranslatorOps - 1 - --- 2018-05-09 Michael Clark New
[v1,4/6] target/riscv: convert to DisasContextBase - 1 - --- 2018-05-09 Michael Clark New
[v1,3/6] target/riscv: convert to DisasJumpType - 2 - --- 2018-05-09 Michael Clark New
[v1,2/6] translator: merge max_insns into DisasContextBase - 1 - --- 2018-05-09 Michael Clark New
[v1,1/6] target/riscv: avoid integer overflow in next_page PC check 1 2 - --- 2018-05-09 Michael Clark New
[v1] RISC-V: Add misa to DisasContext - 2 - --- 2018-05-09 Michael Clark New
[PULL,3/3] riscv: requires libfdt - 3 - --- 2018-05-08 Michael Clark New
[PULL,2/3] riscv: htif: increase the priority of the htif subregion - 1 - --- 2018-05-08 Michael Clark New
[PULL,1/3] riscv: spike: allow base == 0 - 1 - --- 2018-05-08 Michael Clark New
[PULL,3/3] riscv: requires libfdt - 3 - --- 2018-05-07 Michael Clark New
[PULL,2/3] riscv: htif: increase the priority of the htif subregion - 1 - --- 2018-05-07 Michael Clark New
[PULL,1/3] riscv: spike: allow base == 0 - 1 - --- 2018-05-07 Michael Clark New
[PULL,20/20] RISC-V: Mark ROM read-only after copying in code - 1 - --- 2018-05-05 Michael Clark New
[PULL,19/20] RISC-V: No traps on writes to misa, minstret, mcycle - - - --- 2018-05-05 Michael Clark New
[PULL,18/20] RISC-V: Make mtvec/stvec ignore vectored traps - - - --- 2018-05-05 Michael Clark New
[PULL,17/20] RISC-V: Add mcycle/minstret support for -icount auto - 1 - --- 2018-05-05 Michael Clark New
[PULL,16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 - - - --- 2018-05-05 Michael Clark New
[PULL,15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 - 1 - --- 2018-05-05 Michael Clark New
[PULL,14/20] RISC-V: Clear mtval/stval on exceptions without info - 1 - --- 2018-05-05 Michael Clark New
[PULL,13/20] RISC-V: Hardwire satp to 0 for no-mmu case - 1 - --- 2018-05-05 Michael Clark New
[PULL,12/20] RISC-V: Update E and I extension order - 1 - --- 2018-05-05 Michael Clark New
[PULL,11/20] RISC-V: Remove erroneous comment from translate.c - 2 - --- 2018-05-05 Michael Clark New
[PULL,10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection - 2 - --- 2018-05-05 Michael Clark New
[PULL,09/20] RISC-V: Make virt header comment title consistent - 2 - --- 2018-05-05 Michael Clark New
[PULL,08/20] RISC-V: Make some header guards more specific - 2 - --- 2018-05-05 Michael Clark New
[PULL,07/20] RISC-V: Fix missing break statement in disassembler - 2 - --- 2018-05-05 Michael Clark New
[PULL,06/20] RISC-V: Include instruction hex in disassembly - 2 - --- 2018-05-05 Michael Clark New
[PULL,05/20] RISC-V: Remove unused class definitions - 2 - --- 2018-05-05 Michael Clark New
[PULL,04/20] RISC-V: Remove identity_translate from load_elf - 2 - --- 2018-05-05 Michael Clark New
[PULL,03/20] RISC-V: Use ROM base address and size from memmap - 2 - --- 2018-05-05 Michael Clark New
[PULL,02/20] RISC-V: Make virt board description match spike - 2 - --- 2018-05-05 Michael Clark New
[PULL,01/20] RISC-V: Replace hardcoded constants with enum values - 2 - --- 2018-05-05 Michael Clark New
device_tree: Add qemu_fdt_totalsize function - - - --- 2018-05-04 Michael Clark New
RISC-V: Fix missing break statement in disassembler - 2 - --- 2018-04-29 Michael Clark New
[v8,35/35] RISC-V: Use riscv prefix consistently on cpu helpers - - - --- 2018-04-25 Michael Clark New
[v8,34/35] RISC-V: Add hartid and \n to interrupt logging - 1 - --- 2018-04-25 Michael Clark New
[v8,33/35] RISC-V: Add public API for the CSR dispatch table - - - --- 2018-04-25 Michael Clark New
[v8,32/35] RISC-V: Implement mstatus.TSR/TW/TVM - - - --- 2018-04-25 Michael Clark New
[v8,31/35] RISC-V: Mark mstatus.fs dirty - - - --- 2018-04-25 Michael Clark New
[v8,30/35] RISC-V: Split out mstatus_fs from tb_flags - - - --- 2018-04-25 Michael Clark New
[v8,29/35] RISC-V: Implement existential predicates for CSRs 1 - - --- 2018-04-25 Michael Clark New
[v8,28/35] RISC-V: Implement atomic mip/sip CSR updates - 1 - --- 2018-04-25 Michael Clark New
[v8,27/35] RISC-V: Implement modular CSR helper interface - - - --- 2018-04-25 Michael Clark New
[v8,26/35] RISC-V: Update CSR and interrupt definitions - 1 - --- 2018-04-25 Michael Clark New
[v8,25/35] RISC-V: Move non-ops from op_helper to cpu_helper - 1 - --- 2018-04-25 Michael Clark New
[v8,24/35] RISC-V: Allow setting and clearing multiple irqs - - - --- 2018-04-25 Michael Clark New
[v8,23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending - 1 - --- 2018-04-25 Michael Clark New
[v8,22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps - 1 - --- 2018-04-25 Michael Clark New
[v8,21/35] RISC-V: Add mcycle/minstret support for -icount auto - 1 - --- 2018-04-25 Michael Clark New
[v8,20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 - - - --- 2018-04-25 Michael Clark New
[v8,19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 - 1 - --- 2018-04-25 Michael Clark New
[v8,18/35] RISC-V: Clear mtval/stval on exceptions without info - 1 - --- 2018-04-25 Michael Clark New
[v8,17/35] RISC-V: No traps on writes to misa, minstret, mcycle - - - --- 2018-04-25 Michael Clark New
[v8,16/35] RISC-V: Make mtvec/stvec ignore vectored traps - - - --- 2018-04-25 Michael Clark New
[v8,15/35] RISC-V: Hardwire satp to 0 for no-mmu case - 1 - --- 2018-04-25 Michael Clark New
[v8,14/35] RISC-V: Update E order and I extension order - 1 - --- 2018-04-25 Michael Clark New
[v8,13/35] RISC-V: Improve page table walker spec compliance - 1 - --- 2018-04-25 Michael Clark New
[v8,12/35] RISC-V: Update address bits to support sv39 and sv48 - - - --- 2018-04-25 Michael Clark New
[v8,11/35] RISC-V: Mark ROM read-only after copying in code - - - --- 2018-04-25 Michael Clark New
[v8,10/35] RISC-V: Remove erroneous comment from translate.c - 2 - --- 2018-04-25 Michael Clark New
[v8,09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection - 2 - --- 2018-04-25 Michael Clark New
[v8,08/35] RISC-V: Make virt header comment title consistent - 2 - --- 2018-04-25 Michael Clark New
[v8,07/35] RISC-V: Make some header guards more specific - 2 - --- 2018-04-25 Michael Clark New
[v8,06/35] RISC-V: Include instruction hex in disassembly - 2 - --- 2018-04-25 Michael Clark New
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