Show patches with: Submitter = Tommy Wu       |   42 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v6,5/5] target/riscv: Add Smrnmi cpu extension. target/riscv: Add Smrnmi support. - - - --- 2024-09-02 Tommy Wu New
[v6,4/5] target/riscv: Add Smrnmi mnret instruction. target/riscv: Add Smrnmi support. - - - --- 2024-09-02 Tommy Wu New
[v6,3/5] target/riscv: Add Smrnmi CSRs. target/riscv: Add Smrnmi support. - 1 - --- 2024-09-02 Tommy Wu New
[v6,2/5] target/riscv: Handle Smrnmi interrupt and exception. target/riscv: Add Smrnmi support. - - - --- 2024-09-02 Tommy Wu New
[v6,1/5] target/riscv: Add `ext_smrnmi` in the RISCVCPUConfig. target/riscv: Add Smrnmi support. - 1 - --- 2024-09-02 Tommy Wu New
[v5,5/5] target/riscv: Add Smrnmi cpu extension. target/riscv: Add Smrnmi support. - - - --- 2024-08-09 Tommy Wu New
[v5,4/5] target/riscv: Add Smrnmi mnret instruction. target/riscv: Add Smrnmi support. - - - --- 2024-08-09 Tommy Wu New
[v5,3/5] target/riscv: Add Smrnmi CSRs. target/riscv: Add Smrnmi support. - 1 - --- 2024-08-09 Tommy Wu New
[v5,2/5] target/riscv: Handle Smrnmi interrupt and exception. target/riscv: Add Smrnmi support. - - - --- 2024-08-09 Tommy Wu New
[v5,1/5] target/riscv: Add `ext_smrnmi` in the RISCVCPUConfig. target/riscv: Add Smrnmi support. - 1 - --- 2024-08-09 Tommy Wu New
target/riscv: Align the AIA model to v1.0 ratified spec target/riscv: Align the AIA model to v1.0 ratified spec - 1 - --- 2023-08-16 Tommy Wu New
[v6,3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e Implement the watchdog timer of HiFive 1 rev b. 2 1 - --- 2023-06-27 Tommy Wu New
[v6,2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - 3 - --- 2023-06-27 Tommy Wu New
[v6,1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. 1 1 - --- 2023-06-27 Tommy Wu New
hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. 1 2 - --- 2023-06-09 Tommy Wu New
[v5,3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e Implement the watchdog timer of HiFive 1 rev b. 2 1 - --- 2023-06-08 Tommy Wu New
[v5,2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - 2 - --- 2023-06-08 Tommy Wu New
[v5,1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. 1 1 - --- 2023-06-08 Tommy Wu New
[v4,4/4] target/riscv: Add Smrnmi mnret instruction. target/riscv: Add Smrnmi support. - - - --- 2023-06-08 Tommy Wu New
[v4,3/4] target/riscv: Handle Smrnmi interrupt and exception. target/riscv: Add Smrnmi support. - - - --- 2023-06-08 Tommy Wu New
[v4,2/4] target/riscv: Add Smrnmi CSRs. target/riscv: Add Smrnmi support. - 1 - --- 2023-06-08 Tommy Wu New
[v4,1/4] target/riscv: Add Smrnmi cpu extension. target/riscv: Add Smrnmi support. - - - --- 2023-06-08 Tommy Wu New
[2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu. Refresh the dynamic CSR xml after updating the state of the cpu. - 1 - --- 2023-05-23 Tommy Wu New
[1/2] target/riscv: Add a function to refresh the dynamic CSRs xml. Refresh the dynamic CSR xml after updating the state of the cpu. - 2 - --- 2023-05-23 Tommy Wu New
[v4,3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e Implement the watchdog timer of HiFive 1 rev b. 1 1 - --- 2023-05-23 Tommy Wu New
[v4,2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - 2 - --- 2023-05-23 Tommy Wu New
[v4,1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - 1 - --- 2023-05-23 Tommy Wu New
[v3,4/4] target/riscv: Add Smrnmi mnret instruction. target/riscv: Add Smrnmi support. - - - --- 2023-05-22 Tommy Wu New
[v3,3/4] target/riscv: Handle Smrnmi interrupt and exception. target/riscv: Add Smrnmi support. - - - --- 2023-05-22 Tommy Wu New
[v3,2/4] target/riscv: Add Smrnmi CSRs. target/riscv: Add Smrnmi support. - 1 - --- 2023-05-22 Tommy Wu New
[v3,1/4] target/riscv: Add Smrnmi cpu extension. target/riscv: Add Smrnmi support. - 1 - --- 2023-05-22 Tommy Wu New
hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop. hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop. - 2 - --- 2023-05-19 Tommy Wu New
[v3,3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e Implement the watchdog timer of HiFive 1 rev b. - - - --- 2022-11-30 Tommy Wu New
[v3,2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - 1 - --- 2022-11-30 Tommy Wu New
[v3,1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - - - --- 2022-11-30 Tommy Wu New
[v2,3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e Implement the watchdog timer of HiFive 1 rev b. - - - --- 2022-11-01 Tommy Wu New
[v2,2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - - - --- 2022-11-01 Tommy Wu New
[v2,1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - - - --- 2022-11-01 Tommy Wu New
[3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e Implement the watchdog timer of HiFive 1 rev b. - 1 - --- 2022-09-22 Tommy Wu New
[2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - 2 - --- 2022-09-22 Tommy Wu New
[1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. Implement the watchdog timer of HiFive 1 rev b. - 1 - --- 2022-09-22 Tommy Wu New
include/hw/riscv/sifive_e.h: Fix the type of parent_obj of SiFiveEState. include/hw/riscv/sifive_e.h: Fix the type of parent_obj of SiFiveEState. - 2 - --- 2022-08-19 Tommy Wu New