Show patches with: Submitter = Ajeet Singh       |   158 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v7,17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,15/17] bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,14/17] bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,13/17] bsd-user: Define RISC-V signal handling structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,12/17] bsd-user: Add generic RISC-V64 target definitions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,11/17] bsd-user: Define RISC-V system call structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,10/17] bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,09/17] bsd-user: Add RISC-V thread setup and initialization support bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,08/17] bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,07/17] bsd-user: Add RISC-V signal trampoline setup function bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,06/17] bsd-user: Define RISC-V register structures and register copying bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,04/17] bsd-user: Implement RISC-V TLS register setup bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v7,01/17] bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-16 Ajeet Singh New
[v6,17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,15/17] bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,14/17] bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,13/17] bsd-user: Define RISC-V signal handling structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,12/17] bsd-user: Add generic RISC-V64 target definitions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,11/17] bsd-user: Define RISC-V system call structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,10/17] bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,09/17] bsd-user: Add RISC-V thread setup and initialization support bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,08/17] bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,07/17] bsd-user: Add RISC-V signal trampoline setup function bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,06/17] bsd-user: Define RISC-V register structures and register copying bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,04/17] bsd-user: Implement RISC-V TLS register setup bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v6,01/17] bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-15 Ajeet Singh New
[v5,17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,15/17] bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,14/17] bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,13/17] bsd-user: Define RISC-V signal handling structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,12/17] bsd-user: Add generic RISC-V64 target definitions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,11/17] bsd-user: Define RISC-V system call structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,10/17] bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,09/17] bsd-user: Add RISC-V thread setup and initialization support bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,08/17] bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,07/17] bsd-user: Add RISC-V signal trampoline setup function bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,06/17] bsd-user: Define RISC-V register structures and register copying bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,04/17] bsd-user: Implement RISC-V TLS register setup bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v5,01/17] bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Comprehensive RISCV Support - 1 - --- 2024-09-07 Ajeet Singh New
[v4,17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,15/17] bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,14/17] bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,13/17] bsd-user: Define RISC-V signal handling structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,12/17] bsd-user: Add generic RISC-V64 target definitions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,11/17] bsd-user: Define RISC-V system call structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,10/17] bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,09/17] bsd-user: Add RISC-V thread setup and initialization support bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,08/17] bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,07/17] bsd-user: Add RISC-V signal trampoline setup function bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,06/17] bsd-user: Define RISC-V register structures and register copying bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,04/17] bsd-user: Implement RISC-V TLS register setup bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v4,01/17] bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-28 Ajeet Singh New
[v3,17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,15/17] bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,14/17] bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,13/17] bsd-user: Define RISC-V signal handling structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,12/17] bsd-user: Add generic RISC-V64 target definitions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,11/17] bsd-user: Define RISC-V system call structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,10/17] bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,09/17] bsd-user: Add RISC-V thread setup and initialization support bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,08/17] bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,07/17] bsd-user: Add RISC-V signal trampoline setup function bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,06/17] bsd-user: Define RISC-V register structures and register copying bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,04/17] bsd-user: Implement RISC-V TLS register setup bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v3,01/17] bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-24 Ajeet Singh New
[v2,17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,15/17] bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,14/17] bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,13/17] bsd-user: Define RISC-V signal handling structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,12/17] bsd-user: Add generic RISC-V64 target definitions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,11/17] bsd-user: Define RISC-V system call structures and constants bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,10/17] bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,09/17] bsd-user: Add RISC-V thread setup and initialization support bsd-user: Comprehensive RISCV Support - - - --- 2024-08-16 Ajeet Singh New
[v2,08/17] bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,07/17] bsd-user: Add RISC-V signal trampoline setup function bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,06/17] bsd-user: Define RISC-V register structures and register copying bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,04/17] bsd-user: Implement RISC-V TLS register setup bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
[v2,03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Comprehensive RISCV Support - 1 - --- 2024-08-16 Ajeet Singh New
« 1 2 »