Show patches with: Submitter = Anton Blanchard       |   16 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[12/12] target/riscv: handle overlap in widening instructions with overwrite target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS target/riscv: Fix some RISC-V instruction corner cases - 1 - --- 2025-01-26 Anton Blanchard New
[10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[09/12] target/riscv: handle vwadd.wv form mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[08/12] target/riscv: handle vwadd.vv form mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[07/12] target/riscv: handle vwadd.vx form mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[06/12] target/riscv: handle vzext.vf2 form mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[05/12] target/riscv: handle vslide1down.vx form mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[04/12] target/riscv: handle vadd.vv form mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[03/12] target/riscv: handle vadd.vx form mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[02/12] target/riscv: handle vrgather mask and source overlap target/riscv: Fix some RISC-V instruction corner cases - - - --- 2025-01-26 Anton Blanchard New
[01/12] target/riscv: Source vector registers cannot overlap mask register target/riscv: Fix some RISC-V instruction corner cases - 1 - --- 2025-01-26 Anton Blanchard New
[v2] target/riscv: Add Tenstorrent Ascalon CPU [v2] target/riscv: Add Tenstorrent Ascalon CPU 1 1 - --- 2024-11-13 Anton Blanchard New
target/riscv: Add Tenstorrent Ascalon CPU target/riscv: Add Tenstorrent Ascalon CPU - - - --- 2024-11-08 Anton Blanchard New
[v2] target/riscv: Fix vcompress with rvv_ta_all_1s [v2] target/riscv: Fix vcompress with rvv_ta_all_1s - 2 - --- 2024-10-30 Anton Blanchard New
target/riscv: Fix vcompress with rvv_ta_all_1s target/riscv: Fix vcompress with rvv_ta_all_1s - - - --- 2024-10-30 Anton Blanchard New