Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1037 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,12/12] tests/functional: Convert the RV32-on-RV64 riscv test [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 2 - --- 2024-11-07 Alistair Francis New
[PULL,11/12] target/riscv/kvm: Update kvm exts to Linux v6.11 [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 2 - --- 2024-11-07 Alistair Francis New
[PULL,10/12] target/riscv: Inline unit-stride ld/st and corresponding functions for performance [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 2 - --- 2024-11-07 Alistair Francis New
[PULL,09/12] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructi… [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,08/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride… [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,07/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride… [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,06/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked un… [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,05/12] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,04/12] target/riscv: Set vdata.vm field for vector load/store whole register instructions [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,03/12] hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,02/12] hw/riscv/riscv-iommu: change 'depth' to int [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 1 - --- 2024-11-07 Alistair Francis New
[PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts [PULL,01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts - 3 - --- 2024-11-07 Alistair Francis New
[PULL,00/12] riscv-to-apply queue - - - --- 2024-11-07 Alistair Francis New
[PULL,50/50] target/riscv: Fix vcompress with rvv_ta_all_1s [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,49/50] target/riscv/kvm: clarify how 'riscv-aia' default works [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 - - --- 2024-10-31 Alistair Francis New
[PULL,48/50] target/riscv/kvm: set 'aia_mode' to default in error path [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 - - --- 2024-10-31 Alistair Francis New
[PULL,47/50] docs/specs: add riscv-iommu [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,46/50] qtest/riscv-iommu-test: add init queues test [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 1 - --- 2024-10-31 Alistair Francis New
[PULL,45/50] hw/riscv/riscv-iommu: add DBG support [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,44/50] hw/riscv/riscv-iommu: add ATS support [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 1 - --- 2024-10-31 Alistair Francis New
[PULL,43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 1 - --- 2024-10-31 Alistair Francis New
[PULL,42/50] test/qtest: add riscv-iommu-pci tests [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 1 - --- 2024-10-31 Alistair Francis New
[PULL,41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,40/50] hw/riscv: add riscv-iommu-pci reference device [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,38/50] hw/riscv: add RISC-V IOMMU base emulation [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 1 - --- 2024-10-31 Alistair Francis New
[PULL,37/50] hw/riscv: add riscv-iommu-bits.h [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 3 - --- 2024-10-31 Alistair Francis New
[PULL,36/50] exec/memtxattr: add process identifier to the transaction attributes [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 3 - --- 2024-10-31 Alistair Francis New
[PULL,35/50] target/riscv: Expose zicfiss extension as a cpu property [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 - - --- 2024-10-31 Alistair Francis New
[PULL,33/50] disas/riscv: enable disassembly for zicfiss instructions [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 - - --- 2024-10-31 Alistair Francis New
[PULL,32/50] target/riscv: compressed encodings for sspush and sspopchk [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,31/50] target/riscv: implement zicfiss instructions [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,30/50] target/riscv: update `decode_save_opc` to store extra word2 [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,29/50] target/riscv: AMO operations always raise store/AMO fault [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,28/50] target/riscv: mmu changes for zicfiss shadow stack protection [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,27/50] target/riscv: tb flag for shadow stack instructions [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,26/50] target/riscv: introduce ssp and enabling controls for zicfiss [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,25/50] target/riscv: Add zicfiss extension [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,24/50] target/riscv: Expose zicfilp extension as a cpu property [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,23/50] disas/riscv: enable `lpad` disassembly [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,22/50] target/riscv: zicfilp `lpad` impl and branch tracking [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,20/50] target/riscv: additional code information for sw check [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,19/50] target/riscv: save and restore elp state on priv transitions [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,18/50] target/riscv: Introduce elp state and enabling controls for zicfilp [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,17/50] target/riscv: Add zicfilp extension [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,15/50] hw/char: sifive_uart: Print uart characters async [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 1 --- 2024-10-31 Alistair Francis New
[PULL,14/50] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 3 - --- 2024-10-31 Alistair Francis New
[PULL,13/50] hw/intc/riscv_aplic: Check and update pending when write sourcecfg [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 - - --- 2024-10-31 Alistair Francis New
[PULL,12/50] target/riscv: Set vtype.vill on CPU reset [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,11/50] hw/intc: Don't clear pending bits on IRQ lowering [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,10/50] hw/intc: Make zeroth priority register read-only [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 1 - --- 2024-10-31 Alistair Francis New
[PULL,09/50] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT 1 1 - --- 2024-10-31 Alistair Francis New
[PULL,08/50] target/riscv: Add max32 CPU for RV64 QEMU [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,07/50] target/riscv: Enable RV32 CPU support in RV64 QEMU [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,05/50] target/riscv: Detect sxl to set bit width for RV32 in RV64 [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,03/50] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT - 2 - --- 2024-10-31 Alistair Francis New
[PULL,00/50] riscv-to-apply queue - - - --- 2024-10-31 Alistair Francis New
[PULL,v3,35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,33/35] bsd-user: Implement 'get_mcontext' for RISC-V [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,32/35] bsd-user: Implement RISC-V signal trampoline setup functions [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,31/35] bsd-user: Define RISC-V signal handling structures and constants [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,30/35] bsd-user: Add generic RISC-V64 target definitions [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,29/35] bsd-user: Define RISC-V system call structures and constants [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,28/35] bsd-user: Define RISC-V VM parameters and helper functions [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,27/35] bsd-user: Add RISC-V thread setup and initialization support [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,26/35] bsd-user: Implement RISC-V sysarch system call emulation [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,25/35] bsd-user: Add RISC-V signal trampoline setup function [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,24/35] bsd-user: Define RISC-V register structures and register copying [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,22/35] bsd-user: Implement RISC-V TLS register setup [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,19/35] bsd-user: Implement RISC-V CPU initialization and main loop [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,18/35] hw/intc: riscv-imsic: Fix interrupt state updates. [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,16/35] target/riscv32: Fix masking of physical address [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 2 - --- 2024-10-02 Alistair Francis New
[PULL,v3,15/35] target: riscv: Add Svvptc extension support [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,14/35] hw/riscv: Respect firmware ELF entry point [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,13/35] target/riscv: Add textra matching condition for the triggers [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,12/35] target/riscv: Preliminary textra trigger CSR writting support [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,10/35] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 2 - --- 2024-10-02 Alistair Francis New
[PULL,v3,09/35] target/riscv: Stop timer with infinite timecmp [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,08/35] target/riscv/kvm: Fix the group bit setting of AIA [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,06/35] target/riscv: fix za64rs enabling [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 2 - --- 2024-10-02 Alistair Francis New
[PULL,v3,05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,04/35] tests/acpi: Add expected ACPI SRAT AML file for RISC-V [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) 1 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,03/35] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) 1 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) 1 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) [PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-10-02 Alistair Francis New
[PULL,v3,00/35] riscv-to-apply queue - - - --- 2024-10-02 Alistair Francis New
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