Show patches with: Archived = No       |   2721 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,05/24] scripts: remove erroneous file that breaks git clone on Windows [PULL,01/24] stubs: avoid duplicate symbols in libqemuutil.a - - - --- 2024-10-28 Paolo Bonzini New
[PULL,04/24] target/i386: fix CPUID check for LFENCE and SFENCE [PULL,01/24] stubs: avoid duplicate symbols in libqemuutil.a - - 1 --- 2024-10-28 Paolo Bonzini New
[PULL,03/24] ci: enable rust in the Fedora system build job [PULL,01/24] stubs: avoid duplicate symbols in libqemuutil.a - - - --- 2024-10-28 Paolo Bonzini New
[PULL,02/24] tests: add 'rust' and 'bindgen' to CI package list [PULL,01/24] stubs: avoid duplicate symbols in libqemuutil.a - - - --- 2024-10-28 Paolo Bonzini New
[PULL,01/24] stubs: avoid duplicate symbols in libqemuutil.a [PULL,01/24] stubs: avoid duplicate symbols in libqemuutil.a - 1 1 --- 2024-10-28 Paolo Bonzini New
[PULL,00/24] rust, x86, misc patches for 2024-10-28 - - - --- 2024-10-28 Paolo Bonzini New
[v2] hw/intc/loongarch_ipi: Add safer check about cpu [v2] hw/intc/loongarch_ipi: Add safer check about cpu 1 - - --- 2024-10-28 bibo mao New
MAINTAINERS: Remove myself as reviewer MAINTAINERS: Remove myself as reviewer - 1 - --- 2024-10-28 David Gibson New
spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0 spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0 - - - --- 2024-10-28 Amit Machhiwal New
[v2] configure, meson: deprecate 32-bit MIPS [v2] configure, meson: deprecate 32-bit MIPS - 1 - --- 2024-10-28 Paolo Bonzini New
[6/6] target/i386: Introduce GraniteRapids-v2 model Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-28 Tao Su New
[5/6] target/i386: Add support for AVX10 in CPUID enumeration Add AVX10.1 CPUID support and GraniteRapids-v2 model - - 1 --- 2024-10-28 Tao Su New
[4/6] target/i386: Add feature dependencies for AVX10 Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-28 Tao Su New
[3/6] target/i386: Add CPUID.24 leaf for AVX10 Add AVX10.1 CPUID support and GraniteRapids-v2 model - - 1 --- 2024-10-28 Tao Su New
[2/6] target/i386: add avx10-version property Add AVX10.1 CPUID support and GraniteRapids-v2 model - - 1 --- 2024-10-28 Tao Su New
[1/6] target/i386: Add AVX512 state when AVX10 is supported Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-28 Tao Su New
[v3,3/3] linux-headers: Update to Linux v6.12-rc5 linux-headers: Update to Linux v6.12-rc5 - - - --- 2024-10-28 bibo mao New
[v3,2/3] linux-headers: loongarch: Add kvm_para.h linux-headers: Update to Linux v6.12-rc5 - - - --- 2024-10-28 bibo mao New
[v3,1/3] linux-headers: Add unistd_64.h linux-headers: Update to Linux v6.12-rc5 - - - --- 2024-10-28 bibo mao New
[v5] intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM) field [v5] intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM) field 1 2 - --- 2024-10-28 Duan, Zhenzhong New
[v6,3/3] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V Upgrade ACPI SPCR table to support SPCR table revision 4 format - 1 - --- 2024-10-28 Sia Jee Heng New
[v6,2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format Upgrade ACPI SPCR table to support SPCR table revision 4 format 1 3 - --- 2024-10-28 Sia Jee Heng New
[v6,1/3] qtest: allow SPCR acpi table changes Upgrade ACPI SPCR table to support SPCR table revision 4 format 1 1 - --- 2024-10-28 Sia Jee Heng New
[qemu.git,v2,2/2] docs/devel/reset: add plural 's' docs/devel/reset: add missing words - - - --- 2024-10-27 ~axelheider New
[v2] rust/wrapper.h: define memory_order enum [v2] rust/wrapper.h: define memory_order enum - - - --- 2024-10-27 Manos Pitsidianakis New
configure, meson: deprecate 32-bit MIPS configure, meson: deprecate 32-bit MIPS - - - --- 2024-10-27 Paolo Bonzini New
configure: detect 64-bit MIPS configure: detect 64-bit MIPS 1 - - --- 2024-10-27 Paolo Bonzini New
[v3,9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,8/9] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,7/9] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,6/9] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,5/9] target/mips: Convert Loongson DIV.G opcodes to decodetree target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,4/9] target/mips: Convert Loongson DDIV.G opcodes to decodetree target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,3/9] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP target/mips: Convert Loongson LEXT opcodes to decodetree - 2 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,2/9] target/mips: Simplify Loongson MULTU.G opcode target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,1/9] target/mips: Extract decode_64bit_enabled() helper target/mips: Convert Loongson LEXT opcodes to decodetree - 1 - --- 2024-10-26 Philippe Mathieu-Daudé New
[v4,5/5] block: add test non-active commit with zeroed data block: allow commit to unmap zero blocks - 1 1 --- 2024-10-26 Vincent Vanlaer New
[v4,4/5] block: allow commit to unmap zero blocks block: allow commit to unmap zero blocks - 1 - --- 2024-10-26 Vincent Vanlaer New
[v4,3/5] block: refactor error handling of commit_iteration block: allow commit to unmap zero blocks - 1 - --- 2024-10-26 Vincent Vanlaer New
[v4,2/5] block: move commit_run loop to separate function block: allow commit to unmap zero blocks - 1 - --- 2024-10-26 Vincent Vanlaer New
[v4,1/5] block: get type of block allocation in commit_run block: allow commit to unmap zero blocks - 1 - --- 2024-10-26 Vincent Vanlaer New
target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext - - - --- 2024-10-26 Philippe Mathieu-Daudé New
[v3,4/4] virtio_net: Add the 3rd acceptable situation for Mac setup. virtio_net: Add the check for vdpa's mac address - - - --- 2024-10-26 Cindy Lu New
[v3,3/4] virtio_net: Add the 2rd acceptable situation for Mac setup. virtio_net: Add the check for vdpa's mac address - - - --- 2024-10-26 Cindy Lu New
[v3,2/4] virtio_net: Add the check for vdpa's mac address virtio_net: Add the check for vdpa's mac address - - - --- 2024-10-26 Cindy Lu New
[v3,1/4] vhost_vdpa : Add a new parameter to enable check mac address virtio_net: Add the check for vdpa's mac address - - - --- 2024-10-26 Cindy Lu New
[v3] virtio-pci: correctly set virtio pci queue mem multiplier [v3] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-23 Srujana Challa Changes Requested
[v2] virtio-pci: correctly set virtio pci queue mem multiplier [v2] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-20 Srujana Challa Changes Requested
virtio-pci: correctly set virtio pci queue mem multiplier virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-12 Srujana Challa Changes Requested
cryptodev-vhost-user: add asymmetric crypto support cryptodev-vhost-user: add asymmetric crypto support - - - --- 2023-05-14 Gowrishankar Muthukrishnan Superseded
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v1,1/2] target/riscv: add Zicond as an experimental extension [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v3,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v2,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM 1 - - --- 2022-06-16 Lev Kujawski Superseded
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[v1] error-report: fix g_date_time_format assertion [v1] error-report: fix g_date_time_format assertion - - - --- 2022-04-24 Wang, Haiyue Superseded
[v1] aio-posix: fix build failure io_uring 2.2 [v1] aio-posix: fix build failure io_uring 2.2 - - - --- 2022-02-17 Wang, Haiyue Superseded
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v2,1/2] target/riscv: iterate over a table of decoders [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
[v1,1/2] decodetree: Add an optional predicate-function for decoding [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
target/riscv: Fix position of 'experimental' comment target/riscv: Fix position of 'experimental' comment - 3 - --- 2022-01-06 Philipp Tomsich Accepted
[v10,16/16] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,09/16] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-09-04 Philipp Tomsich Superseded
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