Show patches with: Archived = No       |   2709 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[01/25] fifo32: add peek function NXP i.MX RT595 - - - --- 2024-09-18 Octavian Purdila New
[PULL,v2,6/6] migration/multifd: Fix rb->receivedmap cleanup race [PULL,v2,1/6] tests/qtest/migration: Move a couple of slow tests under g_test_slow - - - --- 2024-09-18 Peter Xu New
[PULL,v2,5/6] migration/savevm: Remove extra load cleanup calls [PULL,v2,1/6] tests/qtest/migration: Move a couple of slow tests under g_test_slow - 1 - --- 2024-09-18 Peter Xu New
[PULL,v2,4/6] softmmu/physmem.c: Keep transaction attribute in address_space_map() [PULL,v2,1/6] tests/qtest/migration: Move a couple of slow tests under g_test_slow - 1 - --- 2024-09-18 Peter Xu New
[PULL,v2,3/6] migration/multifd: Fix loop conditions in multifd_zstd_send_prepare and multifd_zstd_… [PULL,v2,1/6] tests/qtest/migration: Move a couple of slow tests under g_test_slow - - - --- 2024-09-18 Peter Xu New
[PULL,v2,2/6] migration/multifd: Fix build for qatzip [PULL,v2,1/6] tests/qtest/migration: Move a couple of slow tests under g_test_slow - - - --- 2024-09-18 Peter Xu New
[PULL,v2,1/6] tests/qtest/migration: Move a couple of slow tests under g_test_slow [PULL,v2,1/6] tests/qtest/migration: Move a couple of slow tests under g_test_slow - - - --- 2024-09-18 Peter Xu New
[PULL,v2,0/6] Migration 20240917 patches - - - --- 2024-09-18 Peter Xu New
[v6,7/7] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-09-18 Max Chou New
[v6,6/7] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-09-18 Max Chou New
[v6,5/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride loa… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-09-18 Max Chou New
[v6,4/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride who… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-09-18 Max Chou New
[v6,3/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-s… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-09-18 Max Chou New
[v6,2/7] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-09-18 Max Chou New
[v6,1/7] target/riscv: Set vdata.vm field for vector load/store whole register instructions Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-09-18 Max Chou New
util/cutils: Remove unused qemu_get_exec_dir util/cutils: Remove unused qemu_get_exec_dir - - - --- 2024-09-18 Dr. David Alan Gilbert New
[v3,3/3] hw/ssi/pnv_spi: Use local var seq_index instead of get_seq_index(). hw/ssi/pnv_spi: Remove PnvXferBuffer and get_seq_index() - - - --- 2024-09-18 Chalapathi V New
[v3,2/3] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure hw/ssi/pnv_spi: Remove PnvXferBuffer and get_seq_index() - - - --- 2024-09-18 Chalapathi V New
[v3,1/3] MAINTAINERS: Cover PowerPC SPI model in PowerNV section hw/ssi/pnv_spi: Remove PnvXferBuffer and get_seq_index() - 1 - --- 2024-09-18 Chalapathi V New
qemu-timer: Remove unused qemu_clock_get_main_loop_timerlist qemu-timer: Remove unused qemu_clock_get_main_loop_timerlist - - - --- 2024-09-18 Dr. David Alan Gilbert New
[v2] hw: fix memory leak in IRQState allocation [v2] hw: fix memory leak in IRQState allocation - 2 - --- 2024-09-18 Matheus Tavares Bernardino New
crypto: Remove unused DER string functions crypto: Remove unused DER string functions - 1 - --- 2024-09-18 Dr. David Alan Gilbert New
hw/char: Remove unused serial_set_frequency hw/char: Remove unused serial_set_frequency - 1 - --- 2024-09-18 Dr. David Alan Gilbert New
util/iova-tree: Remove deadcode util/iova-tree: Remove deadcode - 2 - --- 2024-09-18 Dr. David Alan Gilbert New
linux-user: Remove unused handle_vm86_fault linux-user: Remove unused handle_vm86_fault - 1 - --- 2024-09-18 Dr. David Alan Gilbert New
[2/2] hw/intc: Don't clear pending bits on IRQ lowering riscv: hw/intc: Fixes for standard conformance - 1 - --- 2024-09-18 Sergey Makarov New
[1/2] hw/intc: Make zeroth priority register read-only riscv: hw/intc: Fixes for standard conformance - 1 - --- 2024-09-18 Sergey Makarov New
[v3] i386/cpu: fixup number of addressable IDs for logical processors in the physical package [v3] i386/cpu: fixup number of addressable IDs for logical processors in the physical package - 1 - --- 2024-09-18 Chuang Xu New
[2/2] .gitlab-ci.d: Make separate collapsible log sections for build and test gitlab-ci: Make separate sections for build and test - 1 - --- 2024-09-18 Peter Maydell New
[1/2] .gitlab-ci.d: Split build and test in cross build job templates gitlab-ci: Make separate sections for build and test - 1 - --- 2024-09-18 Peter Maydell New
util/co-shared-resource: Remove unused co_try_get_from_shres util/co-shared-resource: Remove unused co_try_get_from_shres - - - --- 2024-09-18 Dr. David Alan Gilbert New
hw: Remove unused fw_cfg_init_io hw: Remove unused fw_cfg_init_io - 2 - --- 2024-09-18 Dr. David Alan Gilbert New
hw/sysbus: Remove unused sysbus_mmio_unmap hw/sysbus: Remove unused sysbus_mmio_unmap - 1 - --- 2024-09-18 Dr. David Alan Gilbert New
vhost: Remove unused vhost_dev_{load|save}_inflight vhost: Remove unused vhost_dev_{load|save}_inflight - 3 - --- 2024-09-18 Dr. David Alan Gilbert New
[v3] virtio-pci: correctly set virtio pci queue mem multiplier [v3] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-23 Srujana Challa Changes Requested
[v2] virtio-pci: correctly set virtio pci queue mem multiplier [v2] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-20 Srujana Challa Changes Requested
virtio-pci: correctly set virtio pci queue mem multiplier virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-12 Srujana Challa Changes Requested
cryptodev-vhost-user: add asymmetric crypto support cryptodev-vhost-user: add asymmetric crypto support - - - --- 2023-05-14 Gowrishankar Muthukrishnan Superseded
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v1,1/2] target/riscv: add Zicond as an experimental extension [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v3,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v2,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM 1 - - --- 2022-06-16 Lev Kujawski Superseded
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[v1] error-report: fix g_date_time_format assertion [v1] error-report: fix g_date_time_format assertion - - - --- 2022-04-24 Wang, Haiyue Superseded
[v1] aio-posix: fix build failure io_uring 2.2 [v1] aio-posix: fix build failure io_uring 2.2 - - - --- 2022-02-17 Wang, Haiyue Superseded
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v2,1/2] target/riscv: iterate over a table of decoders [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
[v1,1/2] decodetree: Add an optional predicate-function for decoding [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
target/riscv: Fix position of 'experimental' comment target/riscv: Fix position of 'experimental' comment - 3 - --- 2022-01-06 Philipp Tomsich Accepted
[v10,16/16] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,09/16] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,02/16] target/riscv: fix clzw implementation to operate on arg1 target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,01/16] target/riscv: Introduce temporary in gen_add_uw() target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v9,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-03 Philipp Tomsich Superseded
[v9,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,07/14] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,06/14] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
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